Wafer fill patterns and uses

Abstract

A semiconductor device includes an active region including an element formed in a double etch, double exposure method and an inactive region including one or more fills, at least one of the one or more fills including a cut-away hole formed therein, where the cut-away holes expose a layer in the inactive region used for an endpoint detection.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 an active region including an element formed in a double etch, double exposure method; and   an inactive region including one or more fills, at least one of the one or more fills including a cut-away hole formed therein, where the cut-away holes expose a layer in the inactive region used for an endpoint detection.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a substrate supporting both the active region and the inactive region.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 a first layer disposed over the substrate; and   a second layer disposed over the first layer.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the first layer is a gate oxide layer and the second layer is a gate material. 
     
     
         5 . The semiconductor device of  claim 1 , wherein at least half of the fills do not include cut-away holes. 
     
     
         6 . A semiconductor device, the device comprising:
 an active region containing active circuit elements;   an inactive region, the inactive region including a plurality of fill objects, wherein a first portion of the fill objects include cut-away holes utilized for endpoint detection and a second portion of the fill objects include cut-away holes utilized for varying reflectivity of portions of the device.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the first portion includes between 20 to 50 percent of the fill objects. 
     
     
         8 . The semiconductor device of  claim 6 , wherein first portion is separated from the second portion by at least 0.5 millimeters (mm). 
     
     
         9 . The semiconductor device of  claim 6 , where in the fills forming the first portion are located on top of polysilicon. 
     
     
         10 . The semiconductor device of  claim 6 , wherein the second portion is at least partially located in a shallow trench isolation region. 
     
     
         11 . The semiconductor device of  claim 6 , further comprising:
 a substrate on which the active and inactive regions are formed on.   
     
     
         12 . The semiconductor device of  claim 11 , further comprising:
 a first layer disposed over the substrate; and   a second layer disposed over the first layer.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the first layer is a gate oxide layer and the second layer is a gate material.