Inventor · disambiguated record
Li-Chih Fang
Also filed as: FANG LI-CHIH
16 granted patents·18 pending applications·92 citations·filing 2006–2020
92Inventor score
Top patents by PatentIndex Score
34 records- 0192US9761568B2Thin fan-out multi-chip stacked packages and the method for manufacturing the samePOWERTECH TECHNOLOGY INC·Filed 2016·Granted Sep 12, 2017·12 cites·19 claims
- 0290US10593629B2Semiconductor package with a conductive casing for heat dissipation and electromagnetic interference (EMI) shield and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2018·Granted Mar 17, 2020·9 cites·20 claims
- 0390US7619305B2Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stackingPOWERTECH TECHNOLOGY INC·Filed 2007·Granted Nov 17, 2009·31 cites·24 claims
- 0488US9831219B2Manufacturing method of package structurePOWERTECH TECHNOLOGY INC·Filed 2017·Granted Nov 28, 2017·6 cites·20 claims
- 0583US10276510B2Manufacturing method of package structure having conductive shieldPOWERTECH TECHNOLOGY INC·Filed 2017·Granted Apr 30, 2019·4 cites·20 claims
- 0681US9825010B2Stacked chip package structure and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2017·Granted Nov 21, 2017·4 cites·18 claims
- 0781US9659911B1Package structure and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2016·Granted May 23, 2017·3 cites·20 claims
- 0878US7927919B1Semiconductor packaging method to save interposerPOWERTECH TECHNOLOGY INC·Filed 2009·Granted Apr 19, 2011·11 cites·15 claims
- 0973US10607860B2Package structure and chip structurePOWERTECH TECHNOLOGY INC·Filed 2017·Granted Mar 31, 2020·2 cites·11 claims
- 1072US10431549B2Semiconductor package and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2018·Granted Oct 1, 2019·2 cites·9 claims
- 1170US10840200B2Manufacturing method of chip package structure comprising encapsulant having concave surfacePOWERTECH TECHNOLOGY INC·Filed 2018·Granted Nov 17, 2020·1 cites·15 claims
- 1266US7691676B1Mold array process for semiconductor packagesPOWERTECH TECHNOLOGY INC·Filed 2008·Granted Apr 6, 2010·3 cites·11 claims
- 1362US8304917B2Multi-chip stacked package and its mother chip to save interposerFAN WEN-JENG·Filed 2009·Granted Nov 6, 2012·4 cites·12 claims
- 1457US10950557B2Stacked chip package structure and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2020·Granted Mar 16, 2021·0 cites·13 claims
- 1550US10163834B2Chip package structure comprising encapsulant having concave surfacePOWERTECH TECHNOLOGY INC·Filed 2017·Granted Dec 25, 2018·0 cites·10 claims
- 1647US2010000384A1Method for cutting large-size wafer and apparatus for the samePOWERTECH TECHNOLOGY INC·Filed 2008·Application pending·0 cites
- 1746US2009227048A1Method for die bonding having pick-and-probing featurePOWERTECH TECHNOLOGY INC·Filed 2008·Application pending·0 cites
- 1846US2017287870A1Stacked chip package structure and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2017·Application pending·0 cites
- 1945US2009200685A1Electronic packaging method and apparatusPOWERTECH TECHNOLOGY INC·Filed 2008·Application pending·0 cites
- 2045US2009137069A1Chip packaging process including simpification and mergence of burn-in test and high temperature testPOWERTECH TECHNOLOGY INC·Filed 2007·Application pending·0 cites
- 2143US2008169551A1IC chip package with near substrate scale chip attachmentPOWERTECH TECHNOLOGY INC·Filed 2007·Application pending·0 cites
- 2241US2008099890A1Ball grid array package structurePOWERTECH TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 2341US2007257345A1Package structure to reduce warpagePOWERTECH TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 2441US2020357770A1Semiconductor package and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2019·Application pending·0 cites
- 2540US2020243461A1Semiconductor package and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2019·Application pending·0 cites
- 2640US2020243449A1Package structure and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2019·Application pending·0 cites
- 2739US2007298225A1Circuit substrate with strong adhesionPOWERTECH TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 2839US2008272489A1Package substrate and its solder padPOWERTECH TECHNOLOGY INC·Filed 2007·Application pending·0 cites
- 2938US2007278692A1Structure of semiconductor substrate and molding methodPOWERTECH TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 3038US2020006274A1Semiconductor package and manufacturing method thereofPOWERTECH TECHNOLOGY INC·Filed 2018·Application pending·0 cites
- 3137US2019214367A1Stacked package and a manufacturing method of the samePOWERTECH TECHNOLOGY INC·Filed 2018·Application pending·0 cites
- 3237US2007246814A1Ball Grid array package structurePOWERTECH TECHNOLOGY INC·Filed 2006·Application pending·0 cites
- 3336US9972554B2Wafer level chip scale package having continuous through hole via configuration and fabrication method thereofPOWERTECH TECHNOLOGY INC·Filed 2017·Granted May 15, 2018·0 cites·19 claims
- 3436US2017186711A1Structure and method of fan-out stacked packagesPOWERTECH TECHNOLOGY INC·Filed 2016·Application pending·0 cites
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