Stacked chip package structure and manufacturing method thereof

Abstract

A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are respectively disposed on a plurality of first pads of the first chip, wherein each first stud bump includes a rough surface, and the rough surface of each first stud bump is rougher than a top surface of each first pad. The second chip is disposed on the first chip and exposes the first pads. The pillar bumps are respectively disposed on a plurality of second pads of the second chips. The encapsulant encapsulates the first chip and the second chip and exposes a top surface of each second stud bump. The first conductive vias penetrate the encapsulant and connect the first stud bumps. Each first conductive via covers the rough surface of each first stud bump.

What is claimed is: 
     
         1 . A stacked chip package structure, comprising:
 a first chip having a first active surface and a plurality of first pads disposed on the first active surface;   a plurality of first stud bumps disposed on the first pads;   a second chip disposed on the first chip without covering the first pads, the second chip having a second active surface and a plurality of second pads disposed on the second active surface;   a plurality of pillar bumps disposed on the second pads;   an encapsulant encapsulating the first chip and the second chip and exposing a top surface of each of the second stud bumps; and   a plurality of first conductive vias penetrating the encapsulant and coupled to the first stud bumps.   
     
     
         2 . The stacked chip package structure as claimed in  claim 1 , further comprising a redistribution layer disposed on the encapsulant, wherein the redistribution layer comprises a circuit layer electrically connected to the first chip and the second chip through the first conductive vias and the pillar bumps. 
     
     
         3 . The stacked chip package structure as claimed in  claim 2 , further comprising a passivation layer, wherein the passivation layer is disposed on the redistribution layer, the passivation layer comprises a plurality of openings exposing a part of the redistribution layer. 
     
     
         4 . The stacked chip package structure as claimed in  claim 3 , further comprising a plurality of solder balls, wherein the solder balls are disposed on the openings of the passivation layer and electrically connected to the circuit layer. 
     
     
         5 . The stacked chip package structure as claimed in  claim 1 , further comprising a shielding layer disposed on an outer surface of the encapsulant. 
     
     
         6 . The stacked chip package structure as claimed in  claim 5 , wherein the shielding layer is electrically connected to a ground or a supply voltage of the stacked chip package structure. 
     
     
         7 . The stacked chip package structure as claimed in  claim 1 , wherein each of the first stud bumps comprises a rough surface, the rough surface of each of the first stud bumps is rougher than a top surface of each of the first pads, and each of the first conductive vias covering the rough surface of each of the first stud bumps. 
     
     
         8 . The stacked chip package structure as claimed in  claim 7 , wherein the rough surface comprises a rough knot, and each of the first conductive vias covers the rough knot of each of the first stud bumps. 
     
     
         9 . The stacked chip package structure as claimed in  claim 1 , further comprising a third chip, a plurality of second stud bumps and a plurality of second conductive vias, wherein the third chip has a third active surface and a plurality of third pads disposed on the third active surface, the third chip is disposed on the first chip without covering the first pads, the second chip is disposed on the third chip without covering the third pads, the second stud bumps are disposed on the third pads, and the second conductive vias penetrate the encapsulant and are coupled to the second stud bumps. 
     
     
         10 . The stacked chip package structure as claimed in  claim 1 , wherein the number of the first chip is plural, the first chips are arranged in a side-by-side mariner, and the second chip is disposed on the first chips. 
     
     
         11 . The stacked chip package structure as claimed in  claim 9 , further comprising a plurality of third chips, a plurality of second stud bumps and a plurality of second conductive vias, wherein each of the third chips has a third active surface and a plurality of third pads disposed on the third active surface, the third chips are disposed on the first chips without covering the first pads of the first chips, the second chip is disposed on the third chips without covering the third pads of the third chips, the second stud bumps are disposed on the third pads, and the second conductive vias penetrate the encapsulant and are coupled to the second stud bumps. 
     
     
         12 . A manufacturing method of a stacked chip package structure, comprising:
 disposing a first chip on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface;   disposing a second chip on the first chip, wherein the second chip exposes the first pads and has a second active surface and a plurality of second pads disposed on the second active surface;   forming a plurality of first stud bumps on the first pads;   forming a plurality of pillar bumps on the second pads;   encapsulating the first chip and the second chip by an encapsulant, wherein the encapsulant exposes a top surface of each of the pillar bumps;   forming a plurality of first vias by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps;   forming a conductive layer in the first vias to form a plurality of first conductive vias; and   removing the carrier.   
     
     
         13 . The manufacturing method of the stacked chip package structure as claimed in  claim 12 , further comprising:
 forming a redistribution layer on the encapsulant, wherein the redistribution layer comprises a circuit layer electrically connected to the first chip and the second chip through the first conductive vias and the pillar bumps.   
     
     
         14 . The manufacturing method of the stacked chip package structure as claimed in  claim 13 , further comprising:
 forming a passivation layer on the redistribution layer, wherein the passivation layer comprises a plurality of openings exposing a part of the redistribution layer.   
     
     
         15 . The manufacturing method of the stacked chip package structure as claimed in  claim 14 , further comprising:
 forming a plurality of solder balls on the openings of the passivation layer, wherein the solder balls are electrically connected to the circuit layer.   
     
     
         16 . The manufacturing method of the stacked chip package structure as claimed in  claim 12 , further comprising:
 forming a shielding layer on an outer surface of the encapsulant.   
     
     
         17 . The manufacturing method of the stacked chip package structure as claimed in  claim 12 , wherein a top surface of each of the first stud bumps is roughened by the laser process to form a rough surface, and the conductive layer covers the rough surface of each of the first stud bumps. 
     
     
         18 . The manufacturing method of the stacked chip package structure as claimed in  claim 12 , further comprising:
 disposing a third chip on the first chip without covering the first pads before the second chip is disposed on the first chip, wherein the second chip is disposed on the third chip without covering the third pads, and the third chip has a third active surface and a plurality of third pads disposed on the third active surface;   forming a plurality of second stud bumps on the third pads; and   forming a plurality of second conductive vias penetrating the encapsulant and coupled to the second stud bumps.   
     
     
         19 . The manufacturing method of the stacked chip package structure as claimed in  claim 12 , wherein the number of the first chip is plural, the first chips are arranged in a side-by-side manner, and the second chip is disposed on the first chips. 
     
     
         20 . The manufacturing method of the stacked chip package structure as claimed in  claim 19 , further comprising:
 disposing a plurality of third chips on the first chips without covering the first pads of the first chips before the second chip is disposed on the first chips, wherein the second chip is disposed on the third chips without covering the third pads of the third chips, and each of the third chips has a third active surface and a plurality of third pads disposed on the third active surface;   forming a plurality of second stud bumps on the third pads; and   forming a plurality of second conductive vias penetrating the encapsulant and coupled to the second stud bumps.