Inventor · disambiguated record
Robert M. Houle
Also filed as: HOULE ROBERT · HOULE ROBERT M · HOULE ROBERT MAURICE
24 granted patents·4 pending applications·358 citations·filing 1993–2016
96Inventor score
Top patents by PatentIndex Score
28 records- 0194US7986571B2Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit linesIBM·Filed 2010·Granted Jul 26, 2011·19 cites·10 claims
- 0294US7944229B2Method and apparatus for calibrating internal pulses in an integrated circuitIBM·Filed 2009·Granted May 17, 2011·22 cites·20 claims
- 0393US7830727B2Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit linesIBM·Filed 2008·Granted Nov 9, 2010·29 cites·10 claims
- 0491US9172371B2Majority dominant power scheme for repeated structures and structures thereofIBM·Filed 2013·Granted Oct 27, 2015·8 cites·20 claims
- 0590US9890959B2Universal tile installation mat for uncoupling floor or wall tiles set in mortar from a support surfaceHOULE ROBERT·Filed 2016·Granted Feb 13, 2018·26 cites·22 claims
- 0690US8525546B1Majority dominant power scheme for repeated structures and structures thereofARSOVSKI IGOR·Filed 2012·Granted Sep 3, 2013·11 cites·25 claims
- 0789US8228713B2SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for sameARSOVSKI IGOR·Filed 2010·Granted Jul 24, 2012·13 cites·25 claims
- 0889US7973549B2Method and apparatus for calibrating internal pulses in an integrated circuitIBM·Filed 2007·Granted Jul 5, 2011·15 cites·9 claims
- 0985US7940581B2Method for low power sensing in a multi-port SRAM using pre-discharged bit linesIBM·Filed 2010·Granted May 10, 2011·8 cites·10 claims
- 1084US8233337B2SRAM delay circuit that tracks bitcell characteristicsARSOVSKI IGOR·Filed 2009·Granted Jul 31, 2012·14 cites·25 claims
- 1184US5422835ADigital clock signal multiplier circuitIBM·Filed 1993·Granted Jun 6, 1995·58 cites·20 claims
- 1280US7701801B2Programmable pulsewidth and delay generating circuit for integrated circuitsIBM·Filed 2007·Granted Apr 20, 2010·10 cites·17 claims
- 1378US7042776B2Method and circuit for dynamic read margin control of a memory arrayIBM·Filed 2004·Granted May 9, 2006·28 cites·14 claims
- 1477US5835504ASoft fuses using bist for cache self testIBM·Filed 1997·Granted Nov 10, 1998·46 cites·12 claims
- 1575US9916896B1Ternary content addressable memory (TCAM) for multi bit miss detect circuitGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 13, 2018·4 cites·20 claims
- 1673US9583192B1Matchline precharge architecture for self-reference matchline sensingGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 28, 2017·3 cites·20 claims
- 1771US8582351B2Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stabilityARSOVSKI IGOR·Filed 2010·Granted Nov 12, 2013·4 cites·19 claims
- 1865US9704575B1Content-addressable memory having multiple reference matchlines to reduce latencyGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 11, 2017·2 cites·16 claims
- 1964US7859921B2Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit linesIBM·Filed 2008·Granted Dec 28, 2010·4 cites·10 claims
- 2061US7869302B2Programmable pulsewidth and delay generating circuit for integrated circuitsIBM·Filed 2009·Granted Jan 11, 2011·3 cites·13 claims
- 2160US8611169B2Fine granularity power gatingHOULE ROBERT M·Filed 2011·Granted Dec 17, 2013·3 cites·22 claims
- 2252US5691660AClock synchronization scheme for fractional multiplication systemsIBM·Filed 1995·Granted Nov 25, 1997·27 cites·10 claims
- 2348US2009144504A1STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONSIBM·Filed 2008·Application pending·0 cites
- 2447US2009144507A1APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONSIBM·Filed 2007·Application pending·0 cites
- 2545US2015025857A1Statistical power estimationIBM·Filed 2013·Application pending·0 cites
- 2640US9859006B1Algorithmic N search/M write ternary content addressable memory (TCAM)GLOBALFOUNDRIES INC·Filed 2016·Granted Jan 2, 2018·0 cites·20 claims
- 2733US2008298137A1Method and structure for domino read bit line and set reset latchCHAN YUEN HUNG·Filed 2008·Application pending·0 cites
- 2828US5668983APrecise stopping of a high speed microprocessor clockIBM·Filed 1994·Granted Sep 16, 1997·1 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →