Inventor · disambiguated record
Patrick Press
Also filed as: PRESS PATRICK
15 granted patents·6 pending applications·101 citations·filing 1999–2012
91Inventor score
Top patents by PatentIndex Score
21 records- 0194US7741167B2Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strainADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 22, 2010·26 cites·10 claims
- 0290US8247281B2Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayersHEMPEL KLAUS·Filed 2010·Granted Aug 21, 2012·13 cites·18 claims
- 0389US8791509B2Multiple gate transistor having homogenously silicided fin end portionsBEYER SVEN·Filed 2009·Granted Jul 29, 2014·20 cites·20 claims
- 0485US7799682B2Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistorGLOBALFOUNDRIES INC·Filed 2007·Granted Sep 21, 2010·12 cites·13 claims
- 0579US7893503B2Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strainADVANCED MICRO DEVICES INC·Filed 2010·Granted Feb 22, 2011·4 cites·9 claims
- 0677US7605045B2Field effect transistors and methods for fabricating the sameADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 20, 2009·7 cites·17 claims
- 0776US8039335B2Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strainADVANCED MICRO DEVICES INC·Filed 2011·Granted Oct 18, 2011·3 cites·3 claims
- 0873US7745334B2Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniquesADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 29, 2010·4 cites·17 claims
- 0967US8293610B2Semiconductor device comprising a metal gate stack of reduced height and method of forming the sameBEYER SVEN·Filed 2008·Granted Oct 23, 2012·3 cites·18 claims
- 1062US7754554B2Methods for fabricating low contact resistance CMOS circuitsGLOBALFOUNDRIES INC·Filed 2007·Granted Jul 13, 2010·1 cites·19 claims
- 1149US8357575B2Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayersGLOBALFOUNDRIES INC·Filed 2012·Granted Jan 22, 2013·0 cites·12 claims
- 1249US7833874B2Technique for forming an isolation trench as a stress source for strain engineeringGLOBALFOUNDRIES INC·Filed 2006·Granted Nov 16, 2010·0 cites·12 claims
- 1346US2009032855A1Method for forming a deep trench in an soi device by reducing the shielding effect of the active layer during the deep trench etch processPRESS PATRICK·Filed 2008·Application pending·0 cites
- 1445US2008299733A1Method of forming a semiconductor structure comprising an implantation of ions in a material layer to be etchedPRESS PATRICK·Filed 2008·Application pending·0 cites
- 1543US8188871B2Drive current adjustment for transistors by local gate engineeringHORSTMANN MANFRED·Filed 2009·Granted May 29, 2012·0 cites·26 claims
- 1642US7384877B2Technique for reducing silicide defects by reducing deleterious effects of particle bombardment prior to silicidationADVANCED MICRO DEVICES INC·Filed 2006·Granted Jun 10, 2008·0 cites·21 claims
- 1742US2007281472A1Method of increasing transistor performance by dopant activation after silicidationPRESS PATRICK·Filed 2007·Application pending·0 cites
- 1839US2007200176A1Formation of silicided surfaces for silicon/carbon source/drain regionsKAMMLER THORSTEN·Filed 2006·Application pending·0 cites
- 1938US2006270202A1Technique for reducing silicide non-uniformities by adapting a vertical dopant profileWIRBELEIT FRANK·Filed 2006·Application pending·0 cites
- 2036US2011266625A1Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a LinerGLOBALFOUNDRIES INC·Filed 2010·Application pending·0 cites
- 2128US6548378B1Method of boron doping wafers using a vertical oven systemVISHAY SEMICONDUCTOR ITZEHOE G·Filed 1999·Granted Apr 15, 2003·8 cites·7 claims
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