Inventor · disambiguated record
Tak M. Mak
Also filed as: MAK TAK M · MAK TAK MING
20 granted patents·4 pending applications·660 citations·filing 1996–2020
96Inventor score
Files withINTEL CORP14GLOBALFOUNDRIES INC3A T E SOLUTIONS INC1AT E SOLUTIONS INC1GALIVANCHE RAJESHWAR1
Top patents by PatentIndex Score
24 records- 0195US7278076B2System and scanout circuits with error resilience circuitINTEL CORP·Filed 2005·Granted Oct 2, 2007·37 cites·30 claims
- 0295US7278074B2System and shadow circuits with output joining circuitINTEL CORP·Filed 2005·Granted Oct 2, 2007·45 cites·26 claims
- 0395US6222246B1Flip-chip having an on-chip decoupling capacitorINTEL CORP·Filed 1999·Granted Apr 24, 2001·106 cites·17 claims
- 0495US5621739AMethod and apparatus for buffer self-test and characterizationINTEL CORP·Filed 1996·Granted Apr 15, 1997·184 cites·30 claims
- 0591US7373572B2System pulse latch and shadow pulse latch coupled to output joining circuitINTEL CORP·Filed 2005·Granted May 13, 2008·32 cites·24 claims
- 0691US6885209B2Device testingINTEL CORP·Filed 2002·Granted Apr 26, 2005·56 cites·19 claims
- 0790US8926196B2Method and apparatus for an optical interconnect systemINTEL CORP·Filed 2012·Granted Jan 6, 2015·13 cites·17 claims
- 0888US7188284B2Error detecting circuitINTEL CORP·Filed 2004·Granted Mar 6, 2007·42 cites·28 claims
- 0984US6424926B1Bus signature analyzer and behavioral functional test methodINTEL CORP·Filed 2000·Granted Jul 23, 2002·41 cites·30 claims
- 1083US6629274B1Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output bufferINTEL CORP·Filed 1999·Granted Sep 30, 2003·56 cites·20 claims
- 1180US6975954B2Functional testing of logic circuits that use high-speed linksINTEL CORP·Filed 2003·Granted Dec 13, 2005·23 cites·7 claims
- 1268US10673723B2Systems and methods for dynamically reconfiguring automatic test equipmentA T E SOLUTIONS INC·Filed 2018·Granted Jun 2, 2020·2 cites·26 claims
- 1361US9110134B2Input/output delay testing for devices utilizing on-chip delay generationMAK TAK M·Filed 2012·Granted Aug 18, 2015·2 cites·27 claims
- 1460US8843794B2Method, system and apparatus for evaluation of input/output buffer circuitryNELSON CHRISTOPHER J·Filed 2012·Granted Sep 23, 2014·1 cites·30 claims
- 1559US11557420B2Coupling inductors in an IC device using interconnecting elements with solder caps and resulting devicesGLOBALFOUNDRIES US INC·Filed 2017·Granted Jan 17, 2023·0 cites·9 claims
- 1657US7185247B2Pseudo bus agent to support functional testingINTEL CORP·Filed 2003·Granted Feb 27, 2007·7 cites·26 claims
- 1756US6721216B2Memory addressing structural testINTEL CORP·Filed 2001·Granted Apr 13, 2004·9 cites·19 claims
- 1852US9551741B2Current tests for I/O interface connectorsTHIRUVENGADAM BHARANI·Filed 2011·Granted Jan 24, 2017·1 cites·19 claims
- 1949US2020259730A1System and methods for dynamically reconfiguring automatic test equipmentAT E SOLUTIONS INC·Filed 2020·Application pending·0 cites
- 2045US9646758B2Method of fabricating integrated circuit (IC) devicesGLOBALFOUNDRIES INC·Filed 2015·Granted May 9, 2017·0 cites·11 claims
- 2144US2015228635A1Integrated circuit device having supports for use in a multi-dimensional die stackGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2242US2016111406A1Top-side interconnection substrate for die-to-die interconnectionGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 2341US6757209B2Memory cell structural testINTEL CORP·Filed 2001·Granted Jun 29, 2004·3 cites·22 claims
- 2430US2006052075A1Testing integrated circuits using high bandwidth wireless technologyGALIVANCHE RAJESHWAR·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →