System and methods for dynamically reconfiguring automatic test equipment

Abstract

A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testing can be performed at speeds higher than the ATE was originally designed to accommodate. Synthetic instruments are implemented on a field programmable gate array (FPGA) that operate at higher speeds than COTS instruments and can reach the frequencies that high speed I/O buses use. SIs can be created by configuring the FPGA, with different configurations creating different SIs. A single FPGA can house a number of SIs.

1 - 15 . (canceled) 
     
     
         16 . An apparatus, comprising:
 an interface for an automatic test equipment (ATE);   a field programmable gate array (FPGA) that transmits test signals and receives test responses at speeds above the ATE maximum speed; and   a plurality of synthetic instruments associated with the FPGA that switches between a plurality of configurations, wherein the plurality of synthetic instruments is automatically configurable to perform test functions in accordance with the plurality of configurations associated with different types of test instruments.   
     
     
         17 . The apparatus of  claim 16 , comprising:
 a plurality of memory modules communicatively coupled to the plurality of synthetic instruments and the FPGA, wherein each of the plurality of memory modules comprises instructions for generating a configuration of the FPGA.   
     
     
         18 . The apparatus of  claim 16 , wherein each of the plurality of synthetic instruments is dynamically reconfigurable to perform the plurality of test functions based on a device under test (DUT) or a unit under test (UUT) to which the interface is communicatively coupled. 
     
     
         19 . The apparatus of  claim 16 , wherein the plurality of synthetic instruments to perform the plurality of test functions associated with the different types of test instruments is configured on-the-fly by a test program. 
     
     
         20 . The apparatus of  claim 19 , wherein the plurality of synthetic instruments applies a test signal and receives a test response according to a predetermined timing specified by the test program. 
     
     
         21 . The apparatus of  claim 16 , wherein the FPGA performs at least one of the following actions:
 sends a test signal representative of a faulty signal;   analyzes the test response and automatically modifies the test signal based thereon; or   compresses the test results to facilitate transmission.   
     
     
         22 . The apparatus of  claim 16 , wherein at least one of the plurality of synthetic instruments is programmed to detect interference in a signal path, and wherein the known interference comprises degradation due to connection between the FPGA and the DUT or UUT. 
     
     
         23 . The apparatus of  claim 16 , wherein each of the plurality of synthetic instruments is self-calibrated before testing to ensure hardware and software functionality. 
     
     
         24 . The apparatus of  claim 16 , wherein the plurality of synthetic instruments function as multiple instruments during a single test. 
     
     
         25 . A method, comprising:
 providing an interface for an automatic test equipment (ATE), the interface comprising:
 a field programmable gate array (FPGA) that transmits test signals and receives test responses at speeds above the ATE maximum speed; and 
 a plurality of synthetic instruments associated with the FPGA that switches between a plurality of configurations, wherein the plurality of synthetic instruments is automatically configurable to perform test functions in accordance with the plurality of configurations associated with different types of test instruments. 
   
     
     
         26 . The method of  claim 25 , comprising:
 a plurality of memory modules communicatively coupled to the plurality of synthetic instruments and the FPGA, wherein each of the plurality of memory modules comprises instructions for generating a configuration of the FPGA.   
     
     
         27 . The method of  claim 25 , wherein each of the plurality of synthetic instruments is dynamically reconfigurable to perform the plurality of test functions based on a device under test (DUT) or a unit under test (UUT) to which the interface is communicatively coupled. 
     
     
         28 . The method of  claim 25 , wherein the plurality of synthetic instruments to perform the plurality of test functions associated with the different types of test instruments is configured on-the-fly by a test program. 
     
     
         29 . The method of  claim 28 , wherein the plurality of synthetic instruments applies a test signal and receives a test response according to a predetermined timing specified by the test program. 
     
     
         30 . The method of  claim 25 , wherein the FPGA performs at least one of the following actions:
 sends a test signal representative of a faulty signal;   analyzes the test response and automatically modifies the test signal based thereon; or   compresses the test results to facilitate transmission.   
     
     
         31 . The method of  claim 25 , wherein at least one of the plurality of synthetic instruments is programmed to detect interference in a signal path, and wherein the interference comprises degradation due to connection between the FPGA and the DUT or UUT. 
     
     
         32 . The method of  claim 25 , wherein each of the plurality of synthetic instruments is self-calibrated before testing to ensure hardware and software functionality. 
     
     
         33 . The method of  claim 25 , wherein the plurality of synthetic instruments function as multiple instruments during a single test. 
     
     
         34 . A method, comprising:
 providing, by a processor, a plurality of synthetic instruments in an automatic test equipment (ATE), wherein each of the plurality of synthetic instruments is automatically and dynamically reconfigurable to perform a plurality of test functions;   applying at least one stimulus to a device under test (DUT) device, wherein the at least one stimulus executes at least one type of test function from among a plurality of test functions to be performed on the DUT; and   performing, by each of plurality of synthetic instruments, the at least one identified test function in accordance with a test program created for the external device.   
     
     
         35 . A non-transitory computer-readable storage medium having an executable stored thereon, which when executed, instructs a processor to:
 provide a plurality of synthetic instruments in an automatic test equipment (ATE), wherein each of the plurality of synthetic instruments is automatically and dynamically reconfigurable to perform a plurality of test functions;   apply at least one stimulus to a device under test (DUT) device, wherein the at least one stimulus executes at least one type of test function from among a plurality of test functions to be performed on the DUT; and   perform, by each of plurality of synthetic instruments, the at least one identified test function in accordance with a test program created for the external device.