Inventor · disambiguated record
Kevin R. Winstel
Also filed as: WINSTEL KEVIN · WINSTEL KEVIN R
31 granted patents·4 pending applications·548 citations·filing 1998–2022
96Inventor score
Top patents by PatentIndex Score
35 records- 0199US8563403B1Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation lastFAROOQ MUKTA G·Filed 2012·Granted Oct 22, 2013·184 cites·20 claims
- 0298US9620481B2Substrate bonding with diffusion barrier structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 11, 2017·220 cites·16 claims
- 0396US9064937B2Substrate bonding with diffusion barrier structuresIBM·Filed 2013·Granted Jun 23, 2015·29 cites·11 claims
- 0495US8900885B1Wafer bonding misalignment reductionIBM·Filed 2013·Granted Dec 2, 2014·22 cites·20 claims
- 0591US8765578B2Edge protection of bonded wafers during wafer thinningLA TULIPE JR DOUGLAS C·Filed 2012·Granted Jul 1, 2014·16 cites·17 claims
- 0691US7888723B2Deep trench capacitor in a SOI substrate having a laterally protruding buried strapIBM·Filed 2008·Granted Feb 15, 2011·17 cites·25 claims
- 0790US7575970B2Deep trench capacitor through SOI substrate and methods of formingIBM·Filed 2006·Granted Aug 18, 2009·20 cites·16 claims
- 0888US11458474B2Microfluidic chips with one or more viasIBM·Filed 2018·Granted Oct 4, 2022·3 cites·6 claims
- 0987US8546961B2Alignment marks to enable 3D integrationFAROOQ MUKTA G·Filed 2011·Granted Oct 1, 2013·9 cites·19 claims
- 1086US9536853B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2014·Granted Jan 3, 2017·3 cites·6 claims
- 1186US9059039B2Reducing wafer bonding misalignment by varying thermal treatment prior to bondingIBM·Filed 2013·Granted Jun 16, 2015·6 cites·15 claims
- 1282US9214435B2Via structure for three-dimensional circuit integrationFAROOQ MUKTA G·Filed 2012·Granted Dec 15, 2015·5 cites·17 claims
- 1380US9401303B2Handler wafer removal by use of sacrificial inert layerGLOBALFOUNDRIES INC·Filed 2014·Granted Jul 26, 2016·4 cites·20 claims
- 1479US9536809B2Combination of TSV and back side wiring in 3D integrationIBM·Filed 2015·Granted Jan 3, 2017·3 cites·3 claims
- 1571US10937764B2Three-dimensional microelectronic package with embedded cooling channelsIBM·Filed 2019·Granted Mar 2, 2021·1 cites·17 claims
- 1670US2022362774A1Microfluidic chips with one or more viasIBM·Filed 2022·Application pending·0 cites
- 1769US9543229B2Combination of TSV and back side wiring in 3D integrationIBM·Filed 2013·Granted Jan 10, 2017·2 cites·6 claims
- 1867US8198169B2Deep trench capacitor in a SOI substrate having a laterally protruding buried strapBRODSKY MARYJANE·Filed 2010·Granted Jun 12, 2012·2 cites·12 claims
- 1966US11462512B2Three-dimensional microelectronic package with embedded cooling channelsIBM·Filed 2020·Granted Oct 4, 2022·0 cites·20 claims
- 2065US10615139B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2018·Granted Apr 7, 2020·0 cites·4 claims
- 2164US9378966B2Selective etching of silicon waferIBM·Filed 2014·Granted Jun 28, 2016·1 cites·18 claims
- 2264US9059333B1Facilitating chip dicing for metal-metal bonding and hybrid wafer bondingIBM·Filed 2013·Granted Jun 16, 2015·1 cites·16 claims
- 2363US10211178B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2017·Granted Feb 19, 2019·0 cites·5 claims
- 2462US10020279B2Semiconductor device including built-in crack-arresting film structureIBM·Filed 2016·Granted Jul 10, 2018·0 cites·6 claims
- 2553US2015035169A1Via structure for three-dimensional circuit integrationIBM·Filed 2014·Application pending·0 cites
- 2648US9190303B2Reducing wafer bonding misalignment by varying thermal treatment prior to bondingIBM·Filed 2015·Granted Nov 17, 2015·0 cites·5 claims
- 2747US9553054B2Strain detection structures for bonded wafers and chipsIBM·Filed 2014·Granted Jan 24, 2017·0 cites·12 claims
- 2847US9171749B2Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler waferIBM·Filed 2013·Granted Oct 27, 2015·0 cites·18 claims
- 2945US8372725B2Structures and methods of forming pre fabricated deep trench capacitors for SOI substratesIBM·Filed 2010·Granted Feb 12, 2013·0 cites·21 claims
- 3045US2015255417A1Facilitating chip dicing for metal-metal bonding and hybrid wafer bondingIBM·Filed 2015·Application pending·0 cites
- 3143US7560387B2Opening hard mask and SOI substrate in single process chamberIBM·Filed 2006·Granted Jul 14, 2009·0 cites·19 claims
- 3243US2015357207A1Selective etching of silicon waferIBM·Filed 2015·Application pending·0 cites
- 3342US11322361B2Selective etching of silicon waferIBM·Filed 2019·Granted May 3, 2022·0 cites·20 claims
- 3442US10134577B2Edge trim processes and resultant structuresIBM·Filed 2015·Granted Nov 20, 2018·0 cites·17 claims
- 3530US6353246B1Semiconductor device including dislocation in merged SOI/DRAM chipsIBM·Filed 1998·Granted Mar 5, 2002·0 cites·20 claims
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