Assignee
LA TULIPE JR DOUGLAS C
US·3 granted patents·2 pending applications·18 citations·filing 2008–2012
Top patents by PatentIndex Score
5 records- 0191US8765578B2Edge protection of bonded wafers during wafer thinningLA TULIPE JR DOUGLAS C·Filed 2012·Granted Jul 1, 2014·16 cites·17 claims
- 0261US9318375B2Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep viasLA TULIPE JR DOUGLAS C·Filed 2009·Granted Apr 19, 2016·2 cites·11 claims
- 0352US8637953B2Wafer scale membrane for three-dimensional integrated circuit device fabricationLA TULIPE JR DOUGLAS C·Filed 2008·Granted Jan 28, 2014·0 cites·5 claims
- 0452US2012299145A1Apparatus for three-dimensional integrated circuit device fabrication including wafer scale membraneLA TULIPE JR DOUGLAS C·Filed 2012·Application pending·0 cites
- 0552US2012302040A1Method of fabrication of a three-dimensional integrated circuit device using a wafer scale membraneLA TULIPE JR DOUGLAS C·Filed 2012·Application pending·0 cites
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