Via structure for three-dimensional circuit integration

Abstract

Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.

What is claimed is: 
     
         1 . A circuit incorporating three-dimensional integration (3Di) comprising:
 a bottom layer including a bottom landing pad connected to functional components in the bottom layer; and   a plurality of upper layers, stacked above the bottom layer, wherein each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer,   wherein the upper and bottom landing pads are coupled by a single conductive via and wherein the upper and bottom landing pads are aligned in a stack of the bottom layer and the upper layers such that each of the upper and bottom landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.   
     
     
         2 . The circuit of  claim 1 , wherein the landing pads are aligned such that the landing pads are successively offset in one direction. 
     
     
         3 . The circuit of  claim 1 , wherein the landing pads are aligned in a spiral configuration. 
     
     
         4 . The circuit of  claim 1 , wherein at least one of the upper and bottom landing pads includes a conductive liner. 
     
     
         5 . The circuit of  claim 1 , wherein cross-sectional areas of the landing pads that are in contact with the via are equal. 
     
     
         6 . The circuit of  claim 1 , wherein at least two of the upper landing pads includes a respective protective coating and wherein thicknesses of the protective coatings progressively increase from the protective coating of the lowest landing pad of the at least two of the upper landing pads to the protective coating of the highest landing pad of the at least two of the upper landings in the stack. 
     
     
         7 . A wafer multi-stack component incorporating three-dimensional integration (3Di) comprising:
 a bottom wafer including a bottom landing pad connected to functional components in the bottom wafer; and   a plurality of upper wafers, stacked above the bottom wafer, wherein each of the upper wafers includes a respective upper landing pad that is connected to respective functional components in the respective upper wafer,   wherein the landing pads are coupled by a single conductive via and wherein the upper landing pads are aligned in a spiral configuration.   
     
     
         8 . The wafer multi-stack component of  claim 7 , wherein the bottom landing pad is disposed at the center of the spiral configuration. 
     
     
         9 . The wafer multi-stack component of  claim 7 , wherein cross-sectional areas of the landing pads that are in contact with the via are equal. 
     
     
         10 . The wafer multi-stack component of  claim 7 , wherein the bottom wafer and the upper wafers form a stack, wherein each of the upper landing pads of the upper wafers includes a respective protective coating and wherein thicknesses of the protective coatings progressively increase from the protective coating of the upper landing pad of the lowest upper wafer to the protective coating of the upper landing pad of the highest upper wafer in the stack. 
     
     
         11 . An integrated circuit incorporating three-dimensional integration (3Di) comprising:
 a lower layer including a lower landing pad connected to functional components in the lower layer; and   at least one upper layer, stacked above the lower layer, wherein each layer of the at least one upper layer includes a respective upper landing pad that is connected to respective functional components in the respective upper layer,   wherein the upper and lower landing pads are coupled by a single conductive via in a stack formed by the lower layer and the at least one upper layer, wherein each of the upper and lower landing pads includes a respective protective coating and wherein thicknesses of the protective coatings progressively increase from the protective coating of the lower landing pad to the protective coating of the upper landing pad in a top upper layer of the at least one upper layer in the stack.   
     
     
         12 . The integrated circuit of  claim 11 , wherein the upper and lower landing pads are aligned in the stack such that each of the upper and lower landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount. 
     
     
         13 . The integrated circuit of  claim 12 , wherein the upper and lower landing pads are aligned such that the upper and lower landing pads are successively offset in one direction. 
     
     
         14 . The integrated circuit of  claim 12 , wherein the upper and lower landing pads are aligned in a spiral configuration. 
     
     
         15 . The integrated circuit of  claim 12 , wherein the at least one upper layer is a plurality of layers, wherein the upper landing pads of the plurality of layers are aligned in a spiral configuration and wherein the lower landing pad is disposed at the center of the spiral configuration. 
     
     
         16 . The integrated circuit of  claim 11 , wherein cross-sectional areas of the upper and lower landing pads that are in contact with the via are equal.