Inventor · disambiguated record
Lee A. Burton
Also filed as: BURTON LEE · BURTON LEE A
12 granted patents·4 pending applications·238 citations·filing 1994–2013
92Inventor score
Top patents by PatentIndex Score
16 records- 0192US7680968B2Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)SRC COMPUTERS INC·Filed 2007·Granted Mar 16, 2010·27 cites·24 claims
- 0288US7565461B2Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllersSRC COMPUTERS INC·Filed 2005·Granted Jul 21, 2009·20 cites·24 claims
- 0378US7373440B2Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module formatSRC COMPUTERS INC·Filed 2001·Granted May 13, 2008·23 cites·24 claims
- 0477US7003593B2Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface portSRC COMPUTERS INC·Filed 2002·Granted Feb 21, 2006·24 cites·38 claims
- 0575US6295598B1Split directory-based cache coherency technique for a multi-processor computer systemSRC COMPUTERS INC·Filed 1998·Granted Sep 25, 2001·82 cites·22 claims
- 0671US7197575B2Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllersSRC COMPUTERS INC·Filed 2003·Granted Mar 27, 2007·16 cites·51 claims
- 0768US7424552B2Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devicesSRC COMPUTERS INC·Filed 2003·Granted Sep 9, 2008·14 cites·82 claims
- 0866US7421524B2Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module formatSRC COMPUTERS INC·Filed 2004·Granted Sep 2, 2008·9 cites·15 claims
- 0964US6996656B2System and method for providing an arbitrated memory bus in a hybrid computing systemSRC COMPUTERS INC·Filed 2002·Granted Feb 7, 2006·9 cites·12 claims
- 1055US6836823B2Bandwidth enhancement for uncached devicesSRC COMPUTERS INC·Filed 2001·Granted Dec 28, 2004·4 cites·13 claims
- 1150US5455530ADuty cycle control circuit and associated methodCRAY COMPUTER CORP·Filed 1994·Granted Oct 3, 1995·10 cites·14 claims
- 1246US2004236877A1Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)Filed 2004·Application pending·0 cites
- 1346US2005256994A1System and method for providing an arbitrated memory bus in a hybrid computing systemBURTON LEE A·Filed 2005·Application pending·0 cites
- 1445US2006136606A1Logic device comprising reconfigurable core logic for use in conjunction with microprocessor-based computer systemsGUZY D J·Filed 2004·Application pending·0 cites
- 1543US10741226B2Multi-processor computer architecture incorporating distributed multi-ported common memory modulesSAINT REGIS MOHAWK TRIBE·Filed 2013·Granted Aug 11, 2020·0 cites·27 claims
- 1641US2012117318A1Heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (lr-dimms) incorporating isolation memory buffersBURTON LEE A·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →