Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)

Abstract

An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.

What is claimed is:  
     
         1 . A computer system comprising: 
 at least one dense logic device;    a controller for coupling said at least one dense logic device to a control block and a memory bus;    one or more memory module slots coupled to said memory bus, at least one of said one or more memory module slots comprising a buffered memory module;    an adapter port associated with a subset of said one or more memory module slots, said adapter port including associated memory resources; and    at least one direct execution logic element coupled to said adapter port, said memory resources being selectively accessible by said at least one dense logic device and said at least one direct execution logic element.    
     
     
         2 . The computer system of  claim 1  wherein said controller comprises an interleaved memory controller.  
     
     
         3 . The computer system of  claim 1  wherein said buffered memory module comprises an FB-DIMM memory module.  
     
     
         4 . The computer system of  claim 3 , wherein said adapter port comprises an FB-DIMM physical format for retention within one of said memory module slots.  
     
     
         5 . The computer system of  claim 1  wherein said control block provides control information to said adapter port.  
     
     
         6 . The computer system of  claim 1  wherein said control block provides control information to said direct execution logic element.  
     
     
         7 . The computer system of  claim 1  wherein said control block comprises a peripheral bus control block.  
     
     
         8 . The computer system of  claim 7  wherein said peripheral bus control block provides control information to said adapter port.  
     
     
         9 . The computer system of  claim 7  wherein said peripheral control block provides control information to said direct execution logic element.  
     
     
         10 . The computer system of  claim 1  wherein said control block comprises a graphics control block.  
     
     
         11 . The computer system of  claim 10  wherein said graphics control block provides control information to said adapter port.  
     
     
         12 . The computer system of  claim 10  wherein said graphics control block provides control information to said direct execution logic element.  
     
     
         13 . The computer system of  claim 1  wherein said control block comprises a systems maintenance control block.  
     
     
         14 . The computer system of  claim 13  wherein said systems maintenance control block provides control information to said adapter port.  
     
     
         15 . The computer system of  claim 13  wherein said systems maintenance control block provides control information to said direct execution logic element.  
     
     
         16 . The computer system of  claim 1  wherein said direct execution logic element comprises a reconfigurable processor element.  
     
     
         17 . The computer system of  claim 1  wherein said direct execution logic element is operative to alter data received from said controller on said memory bus.  
     
     
         18 . The computer system of  claim 1  wherein said direct execution logic element is operative to alter data received from an external source prior to placing altered data on said memory bus.  
     
     
         19 . The computer system of  claim 1  wherein said direct execution logic element comprises: 
 a control block coupled to said adapter port.  
 
     
     
         20 . The computer system of  claim 19  wherein said direct execution logic element further comprises: 
 at least one field programmable gate array configurable to perform an identified algorithm on and operand provided thereto by said adapter port.  
 
     
     
         21 . The computer system of  claim 20  further comprising: 
 a dual-ported memory block coupling a control block coupled to said adapter port to said at least one field programmable gate array.  
 
     
     
         22 . The computer system of  claim 1  wherein said direct execution logic element comprises: 
 a chain port for coupling said direct execution logic element to another direct execution logic element.  
 
     
     
         23 . The computer system of  claim 19  wherein said direct execution logic element further comprises: 
 a read only memory associated with said control block for providing configuration information thereto.  
 
     
     
         24 . A computer system comprising: 
 at least one dense logic device;    an interleaved controller for coupling said at least one dense logic device to a control block and a memory bus;    a plurality of memory slots coupled to said memory bus, at least one of said plurality of memory slots comprising a buffered memory module;    an adapter port associated with at least two of said plurality of memory slots, each of said adapter port including associated memory resources; and    a direct execution logic element coupled to at least one of said adapter ports, said memory resources being selectively accessible by said at least one dense logic device and said direct execution logic element.    
     
     
         25 . The computer system of  claim 24  wherein said plurality of memory slots comprise FB-DIMM memory module slots.  
     
     
         26 . The computer system of  claim 25  wherein said adapter port comprises an FB-DIMM physical format for retention within one of said FB-DIMM memory module slots.  
     
     
         27 . The computer system of  claim 24  wherein said control block provides control information to said adapter port.  
     
     
         28 . The computer system of  claim 24  wherein said control block provides control information to said direct execution logic element.  
     
     
         29 . The computer system of  claim 24  wherein said control block comprises a peripheral bus control block.  
     
     
         30 . The computer system of  claim 29  wherein said peripheral bus control block provides control information to said adapter port.  
     
     
         31 . The computer system of  claim 29  wherein said peripheral control block provides control information to said direct execution logic element.  
     
     
         32 . The computer system of  claim 24  wherein said control block comprises a graphics control block.  
     
     
         33 . The computer system of  claim 32  wherein said graphics control block provides control information to said adapter port.  
     
     
         34 . The computer system of  claim 32  wherein said graphics control block provides control information to said direct execution logic element.  
     
     
         35 . The computer system of  claim 24  wherein said control block comprises a systems maintenance control block.  
     
     
         36 . The computer system of  claim 35  wherein said systems maintenance control block provides control information to said adapter port.  
     
     
         37 . The computer system of  claim 35  wherein said systems maintenance control block provides control information to said direct execution logic element.  
     
     
         38 . The computer system of  claim 24  wherein said control block comprises a PCI-X control block.  
     
     
         39 . The computer system of  claim 38  wherein said PCI-X control block provides control information to said adapter port.  
     
     
         40 . The computer system of  claim 38  wherein said PCI-X control block provides control information to said direct execution logic element.  
     
     
         41 . The computer system of  claim 24  wherein said control block comprises a PCI Express control block.  
     
     
         42 . The computer system of  claim 41  wherein said PCI Express control block provides control information to said adapter port.  
     
     
         43 . The computer system of  claim 41  wherein said PCI Express control block provides control information to said direct execution logic element.  
     
     
         44 . The computer system of  claim 24  wherein said direct execution logic element comprises a reconfigurable processor element.  
     
     
         45 . The computer system of  claim 24  wherein said direct execution logic element is operative to alter data received from said controller on said memory bus.  
     
     
         46 . The computer system of  claim 24  wherein said direct execution logic element is operative to alter data received from an external source prior to placing altered data on said memory bus.  
     
     
         47 . The computer system of  claim 24  wherein said direct execution logic element comprises: 
 a control block coupled to said adapter port.  
 
     
     
         48 . The computer system of  claim 47  wherein said direct execution logic element further comprises: 
 at least one field programmable gate array configurable to perform an identified algorithm on and operand provided thereto by said adapter port.  
 
     
     
         49 . The computer system of  claim 48  further comprising: 
 a dual-ported memory block coupling a control block coupled to said adapter port to said at least one field programmable gate array.  
 
     
     
         50 . The computer system of  claim 24  wherein said direct execution logic element comprises: 
 a chain port for coupling said processor element to another direct execution logic element.  
 
     
     
         51 . The computer system of  claim 47  wherein said direct execution logic element further comprises: 
 a read only memory associated with said control block for providing configuration information thereto.  
 
     
     
         52 . A computer system including an adapter port for electrical coupling between a memory bus of said computer system and a network interface, said computer system comprising at least one dense logic device coupled to said memory bus through a memory module connector, said adapter port comprising: 
 a memory resource associated with said adapter port; and    a control block for selectively enabling access by said at least one dense logic device to said memory resource.    
     
     
         53 . The computer system of  claim 52  wherein said control block is further operational to selectively preclude access by said at least one dense logic device to said memory resource.  
     
     
         54 . The computer system of  claim 52  further comprising: 
 at least one direct execution logic element coupled to said network interface.  
 
     
     
         55 . The computer system of  claim 54  wherein said control block is further operational to alternatively enable access to said memory resource by said at least one dense logic device and said at least one direct execution logic element.  
     
     
         56 . The computer system of  claim 52  wherein said memory bus further comprises at least one memory module slot and said adapter port is configured for physical retention within said at least one memory module slot through said memory module connector.  
     
     
         57 . The computer system of  claim 56  wherein said at least one memory module slot comprises an FB-DIMM slot.  
     
     
         58 . The computer system of  claim 52  further comprising: 
 an additional adapter port;  
 an additional memory resource associated with said additional adapter port, said control block further operative to selectively enable access by said at least one dense logic device to said additional memory resource.  
 
     
     
         59 . The computer system of  claim 58  wherein said control block is further operational to selectively preclude access by said at least one dense logic device to said memory resource and said additional memory resource.  
     
     
         60 . The computer system of  claim 59  further comprising at least one direct execution logic element coupled to said network interface.  
     
     
         61 . The computer system of  claim 60  wherein said control block is further operational to alternatively enable access to said memory resource and said additional memory resource by said at least one dense logic device and said at least one direct execution logic element.  
     
     
         62 . The computer system of  claim 58  wherein said memory bus further comprises first and second memory module slots for physical retention of said at least one adapter port and said additional adapter port respectively.  
     
     
         63 . The computer system of  claim 62  wherein said first and second memory module slots comprise FB-DIMM slots.  
     
     
         64 . The computer system of  claim 58  wherein said control block is located on a module comprising said adapter port.  
     
     
         65 . The computer system of  claim 52  wherein said computer system further comprises: 
 a memory and I/O controller interposed between said at least one dense logic device and said memory bus.  
 
     
     
         66 . The computer system of  claim 65  wherein said memory and I/O controller comprises an interleaved memory controller.  
     
     
         67 . The computer system of  claim 52  wherein said memory bus comprises address/control and data portions thereof.  
     
     
         68 . The computer system of  claim 52  wherein said memory bus provides address/control and data inputs to said control block to at least partially control its functionality.  
     
     
         69 . The computer system of  claim 52  wherein said control block further comprises a DMA controller for providing direct memory access operations to said memory resource.  
     
     
         70 . The computer system of  claim 69  wherein said DMA controller is fully parameterized.  
     
     
         71 . The computer system of  claim 69  wherein said DMA controller enables scatter/gather functions to be implemented.  
     
     
         72 . The computer system of  claim 69  wherein said DMA controller enables irregular data access pattern functions to be implemented.  
     
     
         73 . The computer system of  claim 69  wherein said DMA controller enables data packing functions to be implemented.  
     
     
         74 . The computer system of  claim 52  wherein said memory resource may be isolated from said memory bus in response to said control block to enable access thereto by a device coupled to said network interface.  
     
     
         75 . The computer system of  claim 52  wherein said memory resource comprises random access memory.  
     
     
         76 . The computer system of  claim 75  wherein said random access memory comprises DRAM.