System and method for providing an arbitrated memory bus in a hybrid computing system

Abstract

A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.

1 . A computing system comprising: 
 at least one microprocessor;    a memory subsystem coupled to the at least one microprocessor;    a memory controller in a chipset of the computing system for issuing read and write commands to the memory subsystem and receiving data that results from the read and write commands coupled to manage memory transactions between the memory subsystem and the at least one microprocessor;    one or more external devices including an independent memory controller for issuing read and write commands to the memory subsystem and receiving data that results from the read and write commands coupled to the memory subsystem so as to have access to the memory subsystem without going through the memory controller; and    at least one arbitration port coupled to the memory controller and configured to receive an external arbitration signal from the one or more external devices, wherein the one or more external devices utilize the external arbitration signal to access the memory subsystem.    
   
   
       2 . The computing system of  claim 1  wherein the arbitration port is implemented in a north bridge component of a system chipset.  
   
   
       3 . The computing system of  claim 2  further comprising: 
 a plurality of interface ports implemented by the north bridge component, each of the plurality of interface ports supporting memory transactions from external systems; and    an arbitration mechanism within the north bridge component for arbitrating amongst the plurality of interface ports for access to the memory subsystem,    wherein the at least one arbitration port couples to the arbitration mechanism.    
   
   
       4 . The computing system of  claim 2  further comprising: 
 a plurality of interface ports implemented by the north bridge component, each of the plurality of interface ports supporting memory transactions from external systems;    an internal arbitration mechanism within the north bridge component for arbitrating amongst the plurality of interface ports for access to the memory subsystem; and    an external arbitration mechanism coupled to provide the arbitration signal over the arbitration port to the internal arbitration mechanism.    
   
   
       5 . The computing system of  claim 1  wherein the arbitration port is implemented in a memory controller.  
   
   
       6 . The computing system of  claim 1  wherein the memory controller is integrated with the at least one microprocessor and the arbitration port is implemented in the memory controller of the microprocessor.  
   
   
       7 . The computing system of  claim 1  wherein one or more external devices access the at least one arbitration port to conduct transactions with the memory subsystem.  
   
   
       8 . A symmetric multiprocessor (SMP) computer system comprising: 
 at least two microprocessors;    a shared system memory;    a memory controller coupled to the shared system memory and the at least two microprocessors for issuing read and write commands to the shared system memory and receiving data that results from the read and write commands wherein the memory controller is implemented in a north bridge component of a system chipset;    one or more external devices including an independent memory controller for issuing read and write commands to the shared system memory and receiving data that results from the read and write commands coupled to the shared system memory such that a data path from the shared system memory to the at least one external device does not pass through the memory controller implemented in the north bridge component; and    a memory arbitration port within the memory controller and configured to receive an external arbitration signal from the one or more external devices to control the data flow of the data path.    
   
   
       9 . The SMP computer system of  claim 8  wherein an arbitration mechanism includes resources for preventing access to specified memory locations by a first of the at least two microprocessors when the specified memory locations are in use by a second of the at least two microprocessors.  
   
   
       10 . The SMP computer system of  claim 8  wherein an arbitration mechanism includes resources for reserving specified memory locations for exclusive access by a subset of the at least two microprocessors.  
   
   
       11 . A computing system comprising: 
 at least one microprocessor;    a memory subsystem;    an IO subsystem;    a memory/IO controller in a chipset of the computing system coupled to manage transactions between the memory subsystem and the I/O subsystem and the at least one microprocessor;    one or more external devices containing independent memory controllers to couple the external devices to the memory subsystem so as to have access to the memory subsystem without utilizing the memory IO controller of the chipset, wherein one of the external devices includes a memory request arbiter; and    at least one arbitration port coupled to the memory/IO controller of the chipset and configured to receive an external arbitration signal from the external device including the request arbiter,    wherein the one or more external devices utilize the external arbitration signal to gain direct access to perform autonomous transactions to the memory subsystem.    
   
   
       12 . The computing system of  claim 11  wherein the arbitration mechanism is implemented in a memory/IO component of a system chipset.  
   
   
       13 . The computing system of  claim 12  further comprising: 
 a plurality of interface ports implemented by the north bridge component, each of the plurality of interface ports supporting memory transactions from external systems; and    an arbitration mechanism within the north bridge component for arbitrating amongst the plurality of interface ports for access to the memory subsystem,    wherein the at least one arbitration port couples to the arbitration mechanism.    
   
   
       14 . The computing system of  claim 12  further comprising: 
 a plurality of interface ports implemented by the north bridge component, each of the plurality of interface ports supporting memory transactions from external systems;    an internal arbitration mechanism within the north bridge component for arbitrating amongst the plurality of interface ports for access to the memory subsystem; and    an external arbitration mechanism coupled to provide the arbitration signal over the arbitration port to the internal arbitration mechanism.    
   
   
       15 . The computing system of  claim 11  wherein the memory controller is integrated with the at least one microprocessor and the request arbiter is implemented in the memory controller of the microprocessor.  
   
   
       16 . A symmetric multiprocessor (SMP) computer system comprising: 
 at least two microprocessors;    a memory subsystem;    a memory/IO controller coupled to the memory subsystem and the at least two microprocessors wherein the memory/IO controller is implemented in a system chipset;    one or more external devices containing memory controllers coupled to the memory subsystem such that the external devices have an independent transaction path to and from the memory;    a memory arbitration port within the memory/IO controller of the chipset and configured to receive an external arbitration signal from the one or more external devices; and    a transaction arbiter in one of the external devices to provide the arbitration control signal to the memory/IO controller in the chipset.    
   
   
       17 . The SMP computer system of  claim 16  wherein an arbitration mechanism includes resources for preventing access to specified memory locations by a first of the at least two microprocessors when the specified memory locations are in use by a second of the at least two microprocessors.  
   
   
       18 . The SMP computer system of  claim 16  wherein an arbitration mechanism includes resources for reserving specified memory locations for exclusive access by a subset of the at least two microprocessors.