Inventor · disambiguated record
Ravi Prakash Srivastava
Also filed as: SRIVASTAVA RAVI · SRIVASTAVA RAVI P · SRIVASTAVA RAVI PRAKASH
31 granted patents·11 pending applications·156 citations·filing 2004–2023
96Inventor score
Files withGLOBALFOUNDRIES INC26GLOBALFOUNDRIES US INC6SRIVASTAVA RAVI PRAKASH4CHARTERED SEMICONDUCTOR MFG1COUNCIL SCIENT IND RES1
Top patents by PatentIndex Score
42 records- 0196US10347528B1Interconnect formation process using wire trench etch prior to via etch, and related interconnectGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 9, 2019·21 cites·12 claims
- 0296US10312188B1Interconnect structure with method of forming the sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 4, 2019·23 cites·17 claims
- 0395US10192780B1Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masksGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 29, 2019·15 cites·20 claims
- 0494US9117822B1Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 25, 2015·16 cites·10 claims
- 0594US8114769B1Methods and structures to enable self-aligned via etch for Cu damascene structure using trench first metal hard mask (TFMHM) schemeSRIVASTAVA RAVI PRAKASH·Filed 2010·Granted Feb 14, 2012·29 cites·20 claims
- 0692US9576894B2Integrated circuits including organic interlayer dielectric layers and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 21, 2017·9 cites·20 claims
- 0788US10692812B2Interconnects with variable space mandrel cuts formed by block patterningGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 23, 2020·4 cites·20 claims
- 0881US10818494B2Metal on metal multiple patterningGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·2 cites·20 claims
- 0980US9691654B1Methods and devices for back end of line via formationGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 27, 2017·3 cites·11 claims
- 1078US10497610B2Dual photoresist approach to lithographic patterning for pitch reductionGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 3, 2019·2 cites·19 claims
- 1176US9362162B2Methods of fabricating BEOL interlayer structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 7, 2016·3 cites·20 claims
- 1275US8932961B2Critical dimension and pattern recognition structures for devices manufactured using double patterning techniquesMEHTA SOHAN·Filed 2012·Granted Jan 13, 2015·5 cites·4 claims
- 1374US10784119B2Multiple patterning with lithographically-defined cutsGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 22, 2020·2 cites·20 claims
- 1473US8420947B2Integrated circuit system with ultra-low k dielectric and method of manufacture thereofSRIVASTAVA RAVI PRAKASH·Filed 2010·Granted Apr 16, 2013·3 cites·20 claims
- 1571US8822342B2Method to reduce depth delta between dense and wide features in dual damascene structuresSRIVASTAVA RAVI PRAKASH·Filed 2010·Granted Sep 2, 2014·3 cites·18 claims
- 1670US10818557B2Integrated circuit structure to reduce soft-fail incidence and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·1 cites·19 claims
- 1767US11398378B2Metal on metal multiple patterningGLOBALFOUNDRIES INC·Filed 2020·Granted Jul 26, 2022·0 cites·20 claims
- 1866US12276831B2Enlarged multilayer nitride waveguide for photonic integrated circuitGLOBALFOUNDRIES US INC·Filed 2022·Granted Apr 15, 2025·0 cites·19 claims
- 1966US10504774B2Lithographic patterning to form fine pitch featuresGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 10, 2019·1 cites·20 claims
- 2063US2025191805A1Structure with barrier-free metal via and metal wire including non-copper conductor, and method to form sameGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 2161US8183149B1Method of fabricating a conductive interconnect arrangement for a semiconductor devicePERMANA DAVID M·Filed 2010·Granted May 22, 2012·2 cites·18 claims
- 2261US8058176B2Methods of patterning insulating layers using etching techniques that compensate for etch rate variationsPARK WAN-JAE·Filed 2007·Granted Nov 15, 2011·3 cites·4 claims
- 2359US12481196B2Optical phase shifter with one or more integrated thermoelectric devicesGLOBALFOUNDRIES US INC·Filed 2023·Granted Nov 25, 2025·0 cites·20 claims
- 2456US2025208341A1Waveguide escalators for a photonics chipGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 2553US10833022B2Structure and method to improve overlay performance in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 10, 2020·0 cites·6 claims
- 2653US7307629B2Generation of three dimensional fractal subsurface structure by Voronoi Tessellation and computation of gravity response of such fractal structureCOUNCIL SCIENT IND RES·Filed 2004·Granted Dec 11, 2007·9 cites·4 claims
- 2752US10770344B2Chamferless interconnect vias of semiconductor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Sep 8, 2020·0 cites·20 claims
- 2852US9293363B2Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 22, 2016·0 cites·7 claims
- 2952US2015050811A1Critical dimension and pattern recognition structures for devices manufactured using double patterning techniquesGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 3051US10714380B2Method of forming smooth sidewall structures using spacer materialsGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·0 cites·20 claims
- 3150US10504851B2Structure and method to improve overlay performance in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 10, 2019·0 cites·20 claims
- 3250US2025149499A1Hybrid bonding with selectively formed dielectric materialGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 3349US10395941B1SADP method with mandrel undercut spacer portion for mandrel space dimension controlGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 27, 2019·0 cites·20 claims
- 3449US2017025347A1Methods and structures for back end of line integrationGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 3546US2009087992A1Method of minimizing via sidewall damages during dual damascene trench reactive ion etching in a via first schemeCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 3645US2023376615A1Network security framework for maintaining data security while allowing remote users to perform user-driven quality analyses of the dataSCHLUMBERGER TECHNOLOGY CORP·Filed 2022·Application pending·0 cites
- 3743US11417525B2Multiple patterning with mandrel cuts defined by block masksGLOBALFOUNDRIES US INC·Filed 2018·Granted Aug 16, 2022·0 cites·8 claims
- 3843US9613909B2Methods and devices for metal filling processesGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 4, 2017·0 cites·12 claims
- 3943US2017186688A1Methods and devices for metal filling processesGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 4040US2019237356A1Air gap formation in back-end-of-line structuresGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 4135US2019079408A1Dual developing methods for lithography patterningGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 4234US2012100716A1Method to improve reliability (EM and TDDB) with post silylation plasma treatment process for copper damascene structuresSRIVASTAVA RAVI PRAKASH·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →