Methods and structures for back end of line integration

Abstract

Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.

What is claimed is: 
     
         1 .- 17 . (canceled) 
     
     
         18 . A semiconductor structure comprising:
 a semiconductor substrate;   a first layer of dielectric disposed on the semiconductor substrate;   a metal region formed on the first layer of dielectric, wherein a portion of the metal region traverses the first layer of dielectric and is in contact with the semiconductor substrate;   a plurality of insulator regions disposed in the metal region, wherein the plurality of insulator regions are comprised of a low-K dielectric.   
     
     
         19 . The semiconductor structure of  claim 18 , wherein each insulator region of the plurality of insulator regions has a width ranging from about 5 nanometers to about 20 nanometers. 
     
     
         20 . The semiconductor structure of  claim 19 , wherein each insulator region of the plurality of insulator regions comprises a void disposed within it. 
     
     
         21 . The semiconductor device of  claim 18 , further comprising:
 a barrier layer disposed between each of the insulator regions and the metal region.   
     
     
         22 . The semiconductor device of  claim 21 , wherein the barrier layer comprises tantalum nitride. 
     
     
         23 . A semiconductor structure, comprising:
 a semiconductor substrate;   a first layer of dielectric disposed on the semiconductor substrate;   a metal region formed on the first layer of dielectric, wherein a portion of the metal region traverses the first layer of dielectric and is in contact with the semiconductor substrate; and   a plurality of insulator regions disposed in the metal region, wherein the plurality of insulator   regions are comprised of a low-K dielectric, and at least one of the insulator regions is disposed on the first layer of dielectric.