Inventor · disambiguated record
David Edward Fisch
Also filed as: FISCH DAVID · FISCH DAVID E · FISCH DAVID EDWARD
49 granted patents·9 pending applications·848 citations·filing 1992–2025
98Inventor score
Files withINVENSAS CORP9XCELSIS CORP8ORBOTECH LTD7ADEIA SEMICONDUCTOR INC5ADEIA SEMICONDUCTOR TECH LLC4
Top patents by PatentIndex Score
58 records- 0199US10991804B2Transistor level interconnection methodologies utilizing 3D interconnectsXCELSIS CORP·Filed 2019·Granted Apr 27, 2021·144 cites·10 claims
- 0299US9812185B2DRAM adjacent row disturb mitigationINVENSAS CORP·Filed 2016·Granted Nov 7, 2017·69 cites·20 claims
- 0398US11127738B2Back biasing of FD-SOI circuit blocksXCELSIS CORP·Filed 2018·Granted Sep 21, 2021·144 cites·18 claims
- 0498US10522352B2Direct-bonded native interconnects and active base dieXCELSIS CORP·Filed 2017·Granted Dec 31, 2019·20 cites·23 claims
- 0598US7542340B2Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating sameINNOVATIVE SILICON ISI SA·Filed 2007·Granted Jun 2, 2009·104 cites·28 claims
- 0696US11823906B2Direct-bonded native interconnects and active base dieADEIA SEMICONDUCTOR INC·Filed 2022·Granted Nov 21, 2023·2 cites·20 claims
- 0796US10832912B2Direct-bonded native interconnects and active base dieXCELSIS CORP·Filed 2019·Granted Nov 10, 2020·10 cites·20 claims
- 0894US11688776B2Transistor level interconnection methodologies utilizing 3D interconnectsADEIA SEMICONDUCTOR INC·Filed 2021·Granted Jun 27, 2023·2 cites·9 claims
- 0992US10262717B2DRAM adjacent row disturb mitigationINVENSAS CORP·Filed 2017·Granted Apr 16, 2019·10 cites·8 claims
- 1091US11599299B23D memory circuitINVENSAS LLC·Filed 2020·Granted Mar 7, 2023·2 cites·14 claims
- 1188US6151236AEnhanced bus turnaround integrated circuit dynamic random access memory deviceENHANCED MEMORY SYSTEMS INC·Filed 2000·Granted Nov 21, 2000·50 cites·7 claims
- 1286US11398258B2Multi-die module with low power operationINVENSAS LLC·Filed 2019·Granted Jul 26, 2022·4 cites·24 claims
- 1386US7969779B2Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating sameMICRON TECHNOLOGY INC·Filed 2009·Granted Jun 28, 2011·10 cites·20 claims
- 1485US12362182B2Direct-bonded native interconnects and active base dieADEIA SEMICONDUCTOR INC·Filed 2023·Granted Jul 15, 2025·0 cites·19 claims
- 1585US11289333B2Direct-bonded native interconnects and active base dieXCELSIS CORP·Filed 2020·Granted Mar 29, 2022·1 cites·26 claims
- 1684US11977211B2Multi-modal wide-angle illumination employing a compound beam combinerORBOTECH LTD·Filed 2020·Granted May 7, 2024·2 cites·24 claims
- 1784US5644545ABimodal refresh circuit and method for using same to reduce standby current and enhance yields of dynamic memory productsUNITED MEMORIES INC·Filed 1996·Granted Jul 1, 1997·58 cites·17 claims
- 1882US12272730B2Transistor level interconnection methodologies utilizing 3D interconnectsADEIA SEMICONDUCTOR INC·Filed 2022·Granted Apr 8, 2025·0 cites·6 claims
- 1981US2025204006A1Transistor level interconnection methodologies utilizing 3d interconnectsADEIA SEMICONDUCTOR INC·Filed 2025·Application pending·0 cites
- 2080US9007866B2Retention optimized memory device using predictive data inversionINVENSAS CORP·Filed 2013·Granted Apr 14, 2015·5 cites·33 claims
- 2179US6822734B1Apparatus and method for fabricating flat workpiecesORBOTECH LTD·Filed 1999·Granted Nov 23, 2004·63 cites·100 claims
- 2278US10455137B2Auto-focus systemORBOTECH LTD·Filed 2014·Granted Oct 22, 2019·4 cites·25 claims
- 2378US2025328278A13d memory circuitADEIA SEMICONDUCTOR TECH LLC·Filed 2025·Application pending·0 cites
- 2477US12293108B23D memory circuitADEIA SEMICONDUCTOR TECH LLC·Filed 2023·Granted May 6, 2025·0 cites·20 claims
- 2577US5254482AFerroelectric capacitor test structure for chip dieNAT SEMICONDUCTOR CORP·Filed 1992·Granted Oct 19, 1993·62 cites·27 claims
- 2676US9153533B2Microelectronic elements with master/slave configurabilityINVENSAS CORP·Filed 2013·Granted Oct 6, 2015·4 cites·16 claims
- 2776US2025038162A1Non-volatile dynamic random access memoryADEIA SEMICONDUCTOR TECH LLC·Filed 2024·Application pending·0 cites
- 2874US6781687B2Illumination and image acquisition systemORBOTECH LTD·Filed 2002·Granted Aug 24, 2004·11 cites·43 claims
- 2973US7619944B2Method and apparatus for variable memory cell refreshINNOVATIVE SILICON ISI SA·Filed 2007·Granted Nov 17, 2009·8 cites·28 claims
- 3072US8462328B2Efficient telecentric optical system (ETOS)FISCH DAVID·Filed 2009·Granted Jun 11, 2013·3 cites·25 claims
- 3171US2024241358A1Multi-Modal Wide-Angle Illumination Employing a Compound Beam CombinerORBOTECH LTD·Filed 2024·Application pending·0 cites
- 3270US8873302B2Common doped region with separate gate control for a logic compatible non-volatile memory cellFISCH DAVID EDWARD·Filed 2011·Granted Oct 28, 2014·3 cites·31 claims
- 3369US8618647B2Packaged microelectronic elements having blind vias for heat dissipationFISCH DAVID EDWARD·Filed 2011·Granted Dec 31, 2013·2 cites·12 claims
- 3469US8064274B2Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling sameFISCH DAVID·Filed 2008·Granted Nov 22, 2011·5 cites·23 claims
- 3566US12113054B2Non-volatile dynamic random access memoryADEIA SEMICONDUCTOR TECH LLC·Filed 2020·Granted Oct 8, 2024·0 cites·19 claims
- 3665US9620433B2Packaged microelectronic elements having blind vias for heat dissipationTESSERA INC·Filed 2013·Granted Apr 11, 2017·1 cites·13 claims
- 3764US8659956B2Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling sameFISCH DAVID·Filed 2011·Granted Feb 25, 2014·2 cites·11 claims
- 3864US8310893B2Techniques for reducing impact of array disturbs in a semiconductor memory deviceLUTHRA YOGESH·Filed 2009·Granted Nov 13, 2012·5 cites·34 claims
- 3963US6301183B1Enhanced bus turnaround integrated circuit dynamic random access memory deviceENHANCED MEMORY SYSTEMS INC·Filed 2000·Granted Oct 9, 2001·12 cites·11 claims
- 4062US2022020741A1Back Biasing of FD-SOI Circuit BlockXCELSIS CORP·Filed 2021·Application pending·0 cites
- 4161US8395937B2Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating sameFISCH DAVID·Filed 2011·Granted Mar 12, 2013·1 cites·22 claims
- 4259US6037827ANoise isolation circuitUNITED MEMORIES INC·Filed 1997·Granted Mar 14, 2000·15 cites·15 claims
- 4358US9299398B2Retention optimized memory device using predictive data inversionINVENSAS CORP·Filed 2015·Granted Mar 29, 2016·1 cites·1 claims
- 4456US9705497B2On-chip impedance network with digital coarse and analog fine tuningINVENSAS CORP·Filed 2015·Granted Jul 11, 2017·1 cites·12 claims
- 4553US9111671B2On-chip impedance network with digital coarse and analog fine tuningDICKE CURTIS·Filed 2013·Granted Aug 18, 2015·1 cites·30 claims
- 4652US6661695B2Capacitance sensing technique for ferroelectric random access memory arraysRAMTRON INT CORP·Filed 2002·Granted Dec 9, 2003·7 cites·9 claims
- 4752US2017207141A1Packaged microelectronic elements having blind vias for heat dissipationTESSERA INC·Filed 2017·Application pending·0 cites
- 4848US9257155B2Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling sameMICRON TECHNOLOGY INC·Filed 2014·Granted Feb 9, 2016·0 cites·19 claims
- 4948US2022005827A1Techniques for manufacturing split-cell 3d-nand memory devicesINVENSAS CORP·Filed 2021·Application pending·0 cites
- 5046US10684929B2Self healing compute arrayXCELSIS CORP·Filed 2017·Granted Jun 16, 2020·0 cites·18 claims
Showing the top 50 of 58 patent records by PatentIndex Score.
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