Assignee
ADEIA SEMICONDUCTOR INC
US·23 granted patents·12 pending applications·69 citations·filing 2018–2025
Top patents by PatentIndex Score
35 records- 0199US11557516B23D chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2020·Granted Jan 17, 2023·7 cites·22 claims
- 0298US11916076B2Device disaggregation for improved performanceADEIA SEMICONDUCTOR INC·Filed 2020·Granted Feb 27, 2024·12 cites·32 claims
- 0398US11515291B2Integrated voltage regulator and passive componentsADEIA SEMICONDUCTOR INC·Filed 2019·Granted Nov 29, 2022·38 cites·18 claims
- 0497US12142528B23D chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2022·Granted Nov 12, 2024·2 cites·26 claims
- 0596US11823906B2Direct-bonded native interconnects and active base dieADEIA SEMICONDUCTOR INC·Filed 2022·Granted Nov 21, 2023·2 cites·20 claims
- 0696US2026052693A13d nand - high aspect ratio strings and channelsADEIA SEMICONDUCTOR INC·Filed 2025·Application pending·0 cites
- 0794US11688776B2Transistor level interconnection methodologies utilizing 3D interconnectsADEIA SEMICONDUCTOR INC·Filed 2021·Granted Jun 27, 2023·2 cites·9 claims
- 0893US12035529B23D NAND—high aspect ratio strings and channelsADEIA SEMICONDUCTOR INC·Filed 2022·Granted Jul 9, 2024·1 cites·10 claims
- 0993US11894345B2Integrated voltage regulator and passive componentsADEIA SEMICONDUCTOR INC·Filed 2022·Granted Feb 6, 2024·1 cites·22 claims
- 1090US11790219B2Three dimensional circuit implementing machine trained networkADEIA SEMICONDUCTOR INC·Filed 2021·Granted Oct 17, 2023·1 cites·22 claims
- 1188US12477738B23D NAND-high aspect ratio strings and channelsADEIA SEMICONDUCTOR INC·Filed 2024·Granted Nov 18, 2025·0 cites·20 claims
- 1288US2025174561A1Stacked ic structure with orthogonal interconnect layersADEIA SEMICONDUCTOR INC·Filed 2024·Application pending·0 cites
- 1387US2025142942A13d chip with shared clock distribution networkADEIA SEMICONDUCTOR INC·Filed 2024·Application pending·0 cites
- 1486US12248869B2Three dimensional circuit implementing machine trained networkADEIA SEMICONDUCTOR INC·Filed 2023·Granted Mar 11, 2025·0 cites·21 claims
- 1586US12218059B2Stacked IC structure with orthogonal interconnect layersADEIA SEMICONDUCTOR INC·Filed 2023·Granted Feb 4, 2025·0 cites·22 claims
- 1686US11881454B2Stacked IC structure with orthogonal interconnect layersADEIA SEMICONDUCTOR INC·Filed 2021·Granted Jan 23, 2024·1 cites·20 claims
- 1786US2026060048A1Direct-bonded native interconnects and active base dieADEIA SEMICONDUCTOR INC·Filed 2025·Application pending·0 cites
- 1885US12362182B2Direct-bonded native interconnects and active base dieADEIA SEMICONDUCTOR INC·Filed 2023·Granted Jul 15, 2025·0 cites·19 claims
- 1985US12293993B23D chip sharing data busADEIA SEMICONDUCTOR INC·Filed 2023·Granted May 6, 2025·0 cites·20 claims
- 2085US12278215B2Integrated voltage regulator and passive componentsADEIA SEMICONDUCTOR INC·Filed 2023·Granted Apr 15, 2025·0 cites·27 claims
- 2184US2025329694A13d chip sharing data busADEIA SEMICONDUCTOR INC·Filed 2025·Application pending·0 cites
- 2282US12272730B2Transistor level interconnection methodologies utilizing 3D interconnectsADEIA SEMICONDUCTOR INC·Filed 2022·Granted Apr 8, 2025·0 cites·6 claims
- 2381US2025204006A1Transistor level interconnection methodologies utilizing 3d interconnectsADEIA SEMICONDUCTOR INC·Filed 2025·Application pending·0 cites
- 2481US2025252299A1Three dimensional circuit implementing machine trained networkADEIA SEMICONDUCTOR INC·Filed 2025·Application pending·0 cites
- 2580US12532594B2Monolithic segmented LED array architecture with islanded epitaxial growthADEIA SEMICONDUCTOR INC·Filed 2024·Granted Jan 20, 2026·0 cites·20 claims
- 2680US2024162190A1Systems and methods for releveled bump planes for chipletsADEIA SEMICONDUCTOR INC·Filed 2023·Application pending·0 cites
- 2779US11914148B2Stacked optical waveguidesADEIA SEMICONDUCTOR INC·Filed 2018·Granted Feb 27, 2024·2 cites·20 claims
- 2879US2025062191A1Hard ip blocks with physically bidirectional passagewaysADEIA SEMICONDUCTOR INC·Filed 2024·Application pending·0 cites
- 2978US2025259970A1Integrated voltage regulator and passive componentsADEIA SEMICONDUCTOR INC·Filed 2025·Application pending·0 cites
- 3076US2024234424A1Device Disaggregation For Improved PerformanceADEIA SEMICONDUCTOR INC·Filed 2024·Application pending·0 cites
- 3175US2024345399A1Stacked optical waveguidesADEIA SEMICONDUCTOR INC·Filed 2024·Application pending·0 cites
- 3273US12401010B23D processor having stacked integrated circuit dieADEIA SEMICONDUCTOR INC·Filed 2021·Granted Aug 26, 2025·0 cites·26 claims
- 3373US11862604B2Systems and methods for releveled bump planes for chipletsADEIA SEMICONDUCTOR INC·Filed 2021·Granted Jan 2, 2024·0 cites·22 claims
- 3473US11824042B23D chip sharing data busADEIA SEMICONDUCTOR INC·Filed 2020·Granted Nov 21, 2023·0 cites·21 claims
- 3571US12074092B2Hard IP blocks with physically bidirectional passagewaysADEIA SEMICONDUCTOR INC·Filed 2021·Granted Aug 27, 2024·0 cites·18 claims
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