Inventor · disambiguated record
Omar M. Shaikh
Also filed as: SHAIKH OMAR · SHAIKH OMAR M
8 granted patents·4 pending applications·27 citations·filing 2010–2017
83Inventor score
Technology areasG06F
Top patents by PatentIndex Score
12 records- 0186US10725755B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsINTEL CORP·Filed 2017·Granted Jul 28, 2020·4 cites·17 claims
- 0279US9672019B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSAGER DAVID J·Filed 2010·Granted Jun 6, 2017·6 cites·18 claims
- 0376US8826257B2Memory disambiguation hardware to support software binary translationAL-OTOOM MUAWYA M·Filed 2012·Granted Sep 2, 2014·7 cites·18 claims
- 0475US9292294B2Detection of memory address aliasing and violations of data dependency relationshipsINTEL CORP·Filed 2012·Granted Mar 22, 2016·4 cites·21 claims
- 0571US9542191B2Hardware profiling mechanism to enable page level automatic binary translationCAPRIOLI PAUL·Filed 2012·Granted Jan 10, 2017·3 cites·20 claims
- 0667US9411739B2System, method and apparatus for improving transactional memory (TM) throughput using TM region indicatorsINTEL CORP·Filed 2012·Granted Aug 9, 2016·1 cites·19 claims
- 0766US9652234B2Instruction and logic to control transfer in a partial binary translation systemCAPRIOLI PAUL·Filed 2011·Granted May 16, 2017·2 cites·25 claims
- 0856US2016350221A1System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory RegionsINTEL CORP·Filed 2016·Application pending·0 cites
- 0956US2017097826A1System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory RegionsSHAIKH OMAR M·Filed 2016·Application pending·0 cites
- 1056US2017097891A1System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory RegionsSHAIKH OMAR M·Filed 2016·Application pending·0 cites
- 1150US9558127B2Instruction and logic for a cache prefetcher and dataless fill bufferINTEL CORP·Filed 2014·Granted Jan 31, 2017·0 cites·17 claims
- 1249US2017212825A1Hardware profiling mechanism to enable page level automatic binary translationINTEL CORP·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →