System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions

Abstract

Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

What is claimed is: 
     
         1 . An apparatus comprising:
 execution circuitry to execute each instruction of a transaction;   a buffer to maintain a mapping from architectural registers to physical registers, wherein the buffer to maintain a plurality of register checkpoints for a plurality of transactional memory (TM) regions by tracking indicators between TM regions to identify a position in the buffer of the last committed instruction and identify a boundary between a youngest TM region and a currently retiring instruction position;   a data cache to store data associated with executed instructions, wherein each entry of the data cache has a bit per TM region indicator to mark memory state of speculative reads wherein a read-bit for a TM region is set when data is speculatively read from that cache line during that transaction and a write-bit is set to indicate when the cache line has speculatively written data.   
     
     
         2 . The apparatus of  claim 1 , wherein the circuitry to assign a transactional memory (TM) region indicator to each instruction of a transaction is allocation circuitry. 
     
     
         3 . The apparatus of  claim 1 , wherein when the transaction commits, read-bits associated with that transaction are cleared. 
     
     
         4 . The apparatus of  claim 1 , wherein when the transaction aborts, read-bits associated with that transaction are cleared and read-bits for any transaction younger than the transaction are also cleared. 
     
     
         5 . The apparatus of  claim 1 , wherein when the transaction commits, write-bits associated with that transaction are cleared. 
     
     
         6 . The apparatus of  claim 1 , wherein read-bits and write-bits associated with a data cache line are stored in the data cache. 
     
     
         7 . A method comprising:
 assigning a transactional memory (TM) region indicator to each instruction of a transaction;   storing previously used physical registers associated with the transaction into a buffer, wherein the buffer maintains a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions;   executing the instructions of the transaction;   retiring one or more oldest load instructions of each TM region from a reorder buffer until a first instruction of an oldest TM region that is not in an initial grouping from that TM region is reached until the oldest TM region has committed; and   setting a read-bit for each load that has been retired into a corresponding data cache entry.   
     
     
         8 . The method of  claim 7 , wherein the assigning occurs during an allocation stage of a pipeline. 
     
     
         9 . The method of claim  87 , wherein the load instructions are retired from a reorder buffer. 
     
     
         10 . The method of  claim 7 , further comprising:
 determining that the transaction is to commit;   committing the transaction;   freeing the previously used physical registers associated with the transaction from the buffer; and   clearing read-bits associated with the transaction from the data cache.   
     
     
         11 . The method of  claim 7 , further comprising:
 determining that the transaction is to not commit;   rolling back to a previous state using the physical registers associated with the transaction from the buffer;   freeing the previously used physical registers associated with the transaction from the buffer; and   clearing read-bits associated with the transaction from the data cache and any read-bits of cache lines that are younger than the transaction.   
     
     
         12 . The method of  claim 7 , wherein the beginning of the transaction is indicated by an instruction. 
     
     
         13 . The method of  claim 7 , wherein the end of the transaction is indicated by an instruction.