System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions

Abstract

Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of cores to perform simultaneous multithreading, at least one of the cores to perform out-of-order instruction execution of instructions of a plurality of threads;   at least one shared cache circuit to be shared among two or more of the cores;   at least one of the cores comprising:
 an instruction fetch circuit to fetch instructions of one or more of the threads; 
 an instruction decode circuit to decode the instructions; 
 a register renaming circuit to rename registers of a register file; 
 an instruction cache to store instructions to be executed; 
 a data cache to store data; 
 at least one buffer to store entries associated with load and store instructions; 
 transaction processing circuitry to process a transactional region of instructions including one or more of the load instructions and store instructions associated with a first transactional region, the transaction processing circuitry to process a transaction begin instruction that indicates a start of the transactional region of instructions and a transaction end instruction that indicates an end of the transactional region of instructions; 
 the transaction processing circuitry to assign a transaction identifier to distinguish between transactional regions; 
 transaction checkpoint circuitry to store an architectural state in response to the start of the transactional region of instructions; 
 transaction status circuitry to store a programmable failure indication associated with a first transaction, wherein the first transaction to fail or proceed based on its associated failure indication, and wherein the programmable failure indication is to indicate failure in response to data loaded by the first transaction being modified by a second transaction; and 
 circuitry to restore the architectural state stored by the transaction checkpoint circuitry in response to a failure of the first transaction. 
   
     
     
         2 . The processor as in  claim 1  wherein the data cache is to store at least one bit associated with a cache line which is to be set when data is speculatively read from the cache line by the transactional region, the at least one bit to identify the cache line as being utilized by the transactional region. 
     
     
         3 . The processor as in  claim 2  wherein the at least at least one bit is to be cleared in response to completion of the transactional region. 
     
     
         4 . The processor as in  claim 1  further comprising:
 an interconnect circuit to couple the processor to one or more system components. 
 
     
     
         5 . A processor comprising:
 simultaneous multithreading means of a plurality of cores to perform out-of-order instruction execution of a plurality of threads;   shared cache means to be shared among two or more of the cores;   at least one of the cores comprising:
 instruction fetch means to fetch instructions of one or more of the threads; 
 instruction decode means to decode the instructions; 
 register renaming means to rename registers of a register file; 
 instruction cache means to store instructions to be executed; 
 data cache means to store data; 
 load/store buffer means to store entries associated with load and store instructions; 
 transaction processing means to process a transactional region of instructions including one or more of the load instructions and store instructions associated with a first transactional region, the transaction processing means to process a transaction begin instruction that indicates a start of the transactional region of instructions and a transaction end instruction that indicates an end of the transactional region of instructions; 
 the transaction processing means to assign a transaction identifier to distinguish between transactional regions; 
 transaction checkpoint means to store an architectural state in response to the start of the transactional region of instructions; 
 transaction status means to store a programmable failure indication associated with a first transaction, wherein the first transaction to fail or proceed based on its associated failure indication, and wherein the programmable failure indication is to indicate failure in response to data loaded by the first transaction being modified by a second transaction; and 
 restore means to restore the architectural state stored by the transaction checkpoint circuitry in response to a failure of the first transaction. 
   
     
     
         6 . The processor as in  claim 5  wherein the data cache means is to store at least one bit associated with a cache line which is to be set when data is speculatively read from the cache line by the transactional region, the at least one bit usable to identify the cache line as being utilized by the transactional region. 
     
     
         7 . The processor as in  claim 6  wherein the at least at least one bit is to be cleared in response to completion of the transactional region. 
     
     
         8 . The processor as in  claim 5  further comprising:
 interconnect means to couple the processor to one or more system components. 
 
     
     
         9 . A method comprising:
 performing simultaneous multithreading of a plurality of threads and out-of-order execution of instructions of the plurality of threads on a plurality of cores;   sharing a cache among two or more of the cores;   fetching instructions of one or more of the threads;   decoding the instructions;   renaming registers of a register file;   storing instructions to be executed in an instruction cache;   storing data in a data cache;   storing entries associated with load and store instructions in a load/store buffer;   processing a transactional region of instructions including one or more of the load instructions and store instructions associated with a first transactional region;   processing a transaction begin instruction that indicates a start of the transactional region of instructions and a transaction end instruction that indicates an end of the transactional region of instructions;   assigning a transaction identifier to distinguish between transactional regions;   storing an architectural state in response to the start of the transactional region of instructions;   storing a programmable failure indication associated with a first transaction, wherein the first transaction to fail or proceed based on its associated failure indication, and wherein the programmable failure indication is to indicate failure in response to data loaded by the first transaction being modified by a second transaction; and   restoring the stored architectural state in response to a failure of the first transaction.   
     
     
         10 . The method as in  claim 9  wherein at least one bit associated with a cache line in the data cache is to be set when data is speculatively read from the cache line by the transactional region, the at least one bit to identify the cache line as being utilized by the transactional region. 
     
     
         11 . The processor as in  claim 10  wherein the at least at least one bit is to be cleared in response to completion of the transactional region. 
     
     
         12 . The processor as in  claim 11  further comprising:
 coupling the processor to one or more system components.