Inventor · disambiguated record
Ryan Sporer
Also filed as: SPORER RYAN W · SPORER RYAN WILLIAM · Sporer Ryan
22 granted patents·5 pending applications·39 citations·filing 2016–2024
92Inventor score
Top patents by PatentIndex Score
27 records- 0194US9806170B1Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOIGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 31, 2017·12 cites·7 claims
- 0293US9634143B1Methods of forming FinFET devices with substantially undoped channel regionsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 25, 2017·11 cites·27 claims
- 0390US11610843B2Well tap for an integrated circuit product and methods of forming such a well tapGLOBALFOUNDRIES US INC·Filed 2021·Granted Mar 21, 2023·2 cites·13 claims
- 0490US10043893B1Post gate silicon germanium channel condensation and method for producing the sameGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 7, 2018·5 cites·5 claims
- 0582US11650382B1Optical components undercut by a sealed cavityGLOBALFOUNDRIES US INC·Filed 2021·Granted May 16, 2023·1 cites·18 claims
- 0682US11409037B2Enlarged waveguide for photonic integrated circuit without impacting interconnect layersGLOBALFOUNDRIES US INC·Filed 2020·Granted Aug 9, 2022·1 cites·20 claims
- 0782US10522655B2Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOIGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 31, 2019·3 cites·7 claims
- 0879US9875936B1Spacer defined fin growth and differential fin widthGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 23, 2018·2 cites·11 claims
- 0977US10217660B2Technique for patterning active regions of transistor elements in a late manufacturing stageGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 26, 2019·2 cites·20 claims
- 1069US12176351B2Photonics chips including a fully-depleted silicon-on-insulator field-effect transistorGLOBALFOUNDRIES US INC·Filed 2022·Granted Dec 24, 2024·0 cites·16 claims
- 1168US12372717B2Structure including hybrid plasmonic waveguide using metal silicide layerGLOBALFOUNDRIES US INC·Filed 2022·Granted Jul 29, 2025·0 cites·20 claims
- 1268US11569268B1Photonics chips including a fully-depleted silicon-on-insulator field-effect transistorGLOBALFOUNDRIES US INC·Filed 2021·Granted Jan 31, 2023·0 cites·18 claims
- 1362US11217678B2Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOIGLOBALFOUNDRIES US INC·Filed 2019·Granted Jan 4, 2022·0 cites·20 claims
- 1457US2025267980A1Photonic devices with thermal isolationGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 1556US2025147235A1Photodetectors with a notched light-absorbing layerGLOBALFOUNDRIES US INC·Filed 2023·Application pending·0 cites
- 1655US10326007B2Post gate silicon germanium channel condensation and method for producing the sameGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 18, 2019·0 cites·11 claims
- 1753US11450573B2Structure with different stress-inducing isolation dielectrics for different polarity FETsGLOBALFOUNDRIES US INC·Filed 2020·Granted Sep 20, 2022·0 cites·18 claims
- 1852US12461312B2Cladding structure in the back end of line of photonics chipsGLOBALFOUNDRIES US INC·Filed 2022·Granted Nov 4, 2025·0 cites·17 claims
- 1952US10943814B1Etch stop member in buried insulator of SOI substrate to reduce contact edge punch throughGLOBALFOUNDRIES US INC·Filed 2019·Granted Mar 9, 2021·0 cites·18 claims
- 2052US2018315832A1Method for late differential soi thinning for improved fdsoi performance and hci optimizationGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 2151US2018130712A1Spacer defined fin growth and differential fin widthGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 2250US11907685B2Structure and method for random code generationGLOBALFOUNDRIES US INC·Filed 2019·Granted Feb 20, 2024·0 cites·20 claims
- 2350US10050119B2Method for late differential SOI thinning for improved FDSOI performance and HCI optimizationGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 14, 2018·0 cites·11 claims
- 2449US11127843B2Asymmetrical lateral heterojunction bipolar transistorsGLOBALFOUNDRIES US INC·Filed 2020·Granted Sep 21, 2021·0 cites·20 claims
- 2549US11094805B2Lateral heterojunction bipolar transistors with asymmetric junctionsGLOBALFOUNDRIES US INC·Filed 2020·Granted Aug 17, 2021·0 cites·20 claims
- 2649US2023146952A1Transistor with faceted, raised source/drain regionGLOBALFOUNDRIES US INC·Filed 2021·Application pending·0 cites
- 2742US10056381B2Punchthrough stop layers for fin-type field-effect transistorsGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 21, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →