Inventor · disambiguated record
Sheila Rima C. Magno
Also filed as: MAGNO SHEILA R C · MAGNO SHEILA RIMA C
9 granted patents·1 pending application·153 citations·filing 2004–2009
89Inventor score
Top patents by PatentIndex Score
10 records- 0193US7148086B2Semiconductor package with controlled solder bump wetting and fabrication method thereforSTATS CHIPPAC LTD·Filed 2005·Granted Dec 12, 2006·27 cites·10 claims
- 0292US7556987B2Method of fabricating an integrated circuit with etched ring and die paddleSTATS CHIPPAC LTD·Filed 2006·Granted Jul 7, 2009·24 cites·4 claims
- 0390US7141886B2Air pocket resistant semiconductor packageSTATS CHIPPAC LTD·Filed 2005·Granted Nov 28, 2006·21 cites·5 claims
- 0490US6969640B1Air pocket resistant semiconductor package systemSTATS CHIPPAC LTD·Filed 2004·Granted Nov 29, 2005·56 cites·8 claims
- 0573US7541222B2Wire sweep resistant semiconductor package and manufacturing method thereforSTATS CHIPPAC LTD·Filed 2006·Granted Jun 2, 2009·5 cites·20 claims
- 0672US8536689B2Integrated circuit package system with multi-surface die attach padDIMAANO JR ANTONIO B·Filed 2005·Granted Sep 17, 2013·8 cites·20 claims
- 0772US8293584B2Integrated circuit package system with filled wafer recessGUILLERMO DENNIS·Filed 2006·Granted Oct 23, 2012·6 cites·20 claims
- 0872US7863108B2Integrated circuit packaging system with etched ring and die paddle and method of manufacture thereofSTATS CHIPPAC LTD·Filed 2009·Granted Jan 4, 2011·4 cites·15 claims
- 0963US7352055B2Semiconductor package with controlled solder bump wettingSTATS CHIPPAC LTD·Filed 2006·Granted Apr 1, 2008·2 cites·6 claims
- 1040US2006043612A1Wire sweep resistant semiconductor package and manufacturing method thereofSTATS CHIPPAC LTD·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →