Inventor · disambiguated record
Sarathy Sribhashyam
Also filed as: SRIBHASHYAM SARATHY · SRIBHASHYAM SARATHY P · SRIBHASHYAM SARATHY PARTHA
9 granted patents·1 pending application·117 citations·filing 1997–2014
89Inventor score
Top patents by PatentIndex Score
10 records- 0188US7405589B2Apparatus and methods for power management in integrated circuitsALTERA CORP·Filed 2005·Granted Jul 29, 2008·13 cites·23 claims
- 0275US6208167B1Voltage tolerant bufferS3 INC·Filed 1997·Granted Mar 27, 2001·33 cites·12 claims
- 0368US8732635B2Apparatus and methods for power management in integrated circuitsLEWIS DAVID·Filed 2008·Granted May 20, 2014·2 cites·20 claims
- 0466US6356509B1System and method for efficiently implementing a double data rate memory architectureSONICBLUE INC·Filed 2000·Granted Mar 12, 2002·20 cites·62 claims
- 0566US5973511AVoltage tolerant input/output bufferS3 INC·Filed 1999·Granted Oct 26, 1999·20 cites·14 claims
- 0651US2014258956A1Apparatus and methods for power management in integrated circuitsALTERA CORP·Filed 2014·Application pending·0 cites
- 0747US6393600B1Skew-independent memory architectureS3 INC·Filed 1999·Granted May 21, 2002·13 cites·15 claims
- 0844US5907249AVoltage tolerant input/output bufferS3 INC·Filed 1997·Granted May 25, 1999·8 cites·5 claims
- 0941US5903180AVoltage tolerant bus hold latchS3 INC·Filed 1997·Granted May 11, 1999·8 cites·32 claims
- 1034US7317340B2Glitch free reset circuitALTERA COPORATION·Filed 2006·Granted Jan 8, 2008·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →