Apparatus and methods for power management in integrated circuits

Abstract

A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

1 - 32 . (canceled) 
     
     
         33 . A computer-implemented method of managing power consumption of an integrated circuit (IC), the method comprising:
 assigning, using the computer, all regions in a set of circuit regions in a design of the integrated circuit as high speed regions;   assigning, using the computer, selectively a subset of regions in the set of circuit regions as low speed regions; and   reverting, using the computer, the assignment of the subset of regions to high speed regions depending on whether a timing specification is met.   
     
     
         34 . The method according to  claim 33 , wherein assigning selectively a subset of regions in the set of circuit regions as low speed regions further comprises:
 successively assigning, using the computer, each region to a low speed region;   performing timing analysis, using the computer, of the design of the integrated circuit; and   re-assigning, using the computer, the region as a high speed region if the design of the integrated circuit, with the region assigned as a low speed region, fails to meet a timing specification.   
     
     
         35 . The method according to  claim 33 , further comprising placing and routing the design of the integrated circuit, using the computer, before assigning selectively a subset of regions in the set of circuit regions as low speed regions. 
     
     
         36 . The method according to  claim 33 , further comprising performing, using the computer, a timing analysis of the design of the integrated circuit before assigning selectively a subset of regions in the set of circuit regions as low speed regions. 
     
     
         37 . The method according to  claim 33 , further comprising selecting, using the computer, at least one supply voltage of the integrated circuit. 
     
     
         38 . The method according to  claim 37 , wherein the supply voltage of the integrated circuit is selected before assigning all regions in a set of circuit regions in a design of the integrated circuit as high speed regions. 
     
     
         39 . The method according to  claim 37 , wherein the supply voltage of the integrated circuit is selected after assignment of the set of circuit regions has concluded. 
     
     
         40 . The method according to  claim 33 , wherein the set of circuit regions corresponds to a set of programmable logic blocks. 
     
     
         41 . The method according to  claim 40 , wherein the set of circuit regions further corresponds to a set of programmable interconnect. 
     
     
         42 . A computer program product comprising computer-readable instructions that, when executed by a computer, cause the computer to:
 assign all regions in a set of circuit regions in a design of an integrated circuit (IC) as high speed regions;   assign selectively a subset of regions in the set of circuit regions as low speed regions; and   revert the assignment of the subset of regions to high speed regions depending on whether a timing specification is met.   
     
     
         43 . The computer program product of  claim 42 , further comprising computer-readable instructions that, when executed by the computer, cause the computer to:
 successively assign each region to a low speed region;   perform timing analysis of the design of the integrated circuit; and   re-assign the region as a high speed region if the design of the integrated circuit, with the region assigned as a low speed region, fails to meet a timing specification.   
     
     
         44 . The computer program product of  claim 42 , further comprising computer-readable instructions that, when executed by the computer, cause the computer to place and route the design of the integrated circuit before assigning selectively a subset of regions in the set of circuit regions as low speed regions. 
     
     
         45 . The computer program product of  claim 42 , further comprising computer-readable instructions that, when executed by the computer, cause the computer to perform a timing analysis of the design of the integrated circuit before assigning selectively a subset of regions in the set of circuit regions as low speed regions. 
     
     
         46 . The computer program product of  claim 42 , further comprising computer-readable instructions that, when executed by the computer, cause the computer to select at least one supply voltage of the integrated circuit. 
     
     
         47 . A computer-aided design (CAD) system for managing power consumption of an integrated circuit (IC), the system comprising a computer to: assign all regions in a set of circuit regions in a design of an integrated circuit (IC) as high speed regions; assign selectively a subset of regions in the set of circuit regions as low speed regions; and revert the assignment of the subset of regions to high speed regions depending on whether a timing specification is met. 
     
     
         48 . The computer-aided design (CAD) system according to  claim 47 , wherein the computer further assigns successively each region to a low speed region; performs timing analysis of the design of the integrated circuit; and re-assigns the region as a high speed region if the design of the integrated circuit, with the region assigned as a low speed region, fails to meet a timing specification. 
     
     
         49 . The computer-aided design (CAD) system according to  claim 47 , wherein the computer further places and routes the design of the integrated circuit before assigning selectively a subset of regions in the set of circuit regions as low speed regions. 
     
     
         50 . The computer-aided design (CAD) system according to  claim 47 , wherein the computer further performs a timing analysis of the design of the integrated circuit before assigning selectively a subset of regions in the set of circuit regions as low speed regions. 
     
     
         51 . The computer-aided design (CAD) system according to  claim 47 , wherein the computer further selects at least one supply voltage of the integrated circuit. 
     
     
         52 . The computer-aided design (CAD) system according to  claim 47 , wherein the computer selects the supply voltage of the integrated circuit after assignment of the set of circuit regions has concluded.