Assignee

S3 INC

US98 patents

Top patents by PatentIndex Score

US5392239AFeb 21, 1995

Burst-mode DRAM

S3 INC194 citations99

US5956431ASep 21, 1999

System and method for fixed-rate block-based image compression with inferred pixel values

S3 INC179 citations98

US5848264ADec 8, 1998

Debug and video queue for multi-processor chip

S3 INC204 citations98

US5828578AOct 27, 1998

Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield

S3 INC109 citations98

US5948083ASep 7, 1999

System and method for self-adjusting data strobe

S3 INC118 citations97

US6076155AJun 13, 2000

Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets

S3 INC73 citations96

US6034733AMar 7, 2000

Timing and control for deinterlacing and enhancement of non-deterministically arriving interlaced video data

S3 INC92 citations96

US6008794ADec 28, 1999

Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity

S3 INC69 citations96

US6044448AMar 28, 2000

Processor having multiple datapath instances

S3 INC81 citations95

US6041419AMar 21, 2000

Programmable delay timing calibrator for high speed data interface

S3 INC74 citations95

US6005412ADec 21, 1999

AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip

S3 INC62 citations95

US5977960ANov 2, 1999

Apparatus, systems and methods for controlling data overlay in multimedia data processing and display systems using mask techniques

S3 INC61 citations95

US5862390AJan 19, 1999

Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer

S3 INC69 citations95

US5778096AJul 7, 1998

Decompression of MPEG compressed data in a computer system

S3 INC53 citations95

US6144365ANov 7, 2000

System and method for performing blending using an over sampling buffer

S3 INC101 citations94

US5990912ANov 23, 1999

Virtual address access to tiled surfaces

S3 INC55 citations94

US6389566B1May 14, 2002

Edge-triggered scan flip-flop and one-pass scan synthesis methodology

S3 INC57 citations93

US6093029AJul 25, 2000

Vertically stackable integrated circuit

S3 INC88 citations93

US6052133AApr 18, 2000

Multi-function controller and method for a computer graphics display system

S3 INC58 citations93

US5935198AAug 10, 1999

Multiplier with selectable booth encoders for performing 3D graphics interpolations with two multiplies in a single pass through the multiplier

S3 INC34 citations93

US5889499AMar 30, 1999

System and method for the mixing of graphics and video signals

S3 INC83 citations93

US5826074AOct 20, 1998

Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register

S3 INC54 citations93

US5748126AMay 5, 1998

Sigma-delta digital-to-analog conversion system and process through reconstruction and resampling

S3 INC79 citations93

US6345099B1Feb 5, 2002

System and method for copy protecting computer graphics

S3 INC22 citations92

US6212490B1Apr 3, 2001

Hybrid circuit model simulator for accurate timing and noise analysis

S3 INC50 citations92

US6172718B1Jan 9, 2001

Adaptive dynamic aperture correction

S3 INC25 citations92

US6141020AOct 31, 2000

Opposing directional fill calculators in a graphics processor

S3 INC23 citations92

US6072508AJun 6, 2000

Method and apparatus for shortening display list instructions

S3 INC24 citations92

US6040737AMar 21, 2000

Output buffer circuit and method that compensate for operating conditions and manufacturing processes

S3 INC43 citations92

US6005432ADec 21, 1999

Voltage level shift system and method

S3 INC24 citations92

US5977933ANov 2, 1999

Dual image computer display controller

S3 INC110 citations92

US5958038ASep 28, 1999

Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation

S3 INC21 citations92

US5914719AJun 22, 1999

Index and storage system for data provided in the vertical blanking interval

S3 INC33 citations92

US5835104ANov 10, 1998

Variable band size compositing buffer method and apparatus

S3 INC22 citations92

US5805918ASep 8, 1998

Dual-instruction-set CPU having shared register for storing data before switching to the alternate instruction set

S3 INC41 citations92

US5790826AAug 4, 1998

Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes

S3 INC32 citations92

US5764240AJun 9, 1998

Method and apparatus for correction of video tearing associated with a video and graphics shared frame buffer, as displayed on a graphics monitor

S3 INC22 citations92

US6208167B1Mar 27, 2001

Voltage tolerant buffer

S3 INC33 citations91

US6175851B1Jan 16, 2001

Fast adder/subtractor for signed floating point numbers

S3 INC22 citations91

US6169418B1Jan 2, 2001

Efficient routing from multiple sources to embedded DRAM and other large circuit blocks

S3 INC40 citations91

US5990965ANov 23, 1999

System and method for simultaneous flicker filtering and overscan compensation

S3 INC22 citations91

US5977983ANov 2, 1999

Method and apparatus for adjusting graphics processing procedures based on a selectable speed/quality gauge

S3 INC39 citations91

US5910820AJun 8, 1999

Correction of flicker associated with noninterlaced-to-interlaced video conversion

S3 INC32 citations91

US5828383AOct 27, 1998

Controller for processing different pixel data types stored in the same display memory by use of tag bits

S3 INC108 citations91

US5793386AAug 11, 1998

Register set reordering for a graphics processor based upon the type of primitive to be rendered

S3 INC48 citations91

US5517626AMay 14, 1996

Open high speed bus for microcomputer system

S3 INC146 citations91

Showing the top 50 of 98 patents by PatentIndex Score.

S3 INC

Top patents by PatentIndex Score

Burst-mode DRAM

System and method for fixed-rate block-based image compression with inferred pixel values

Debug and video queue for multi-processor chip

Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield

System and method for self-adjusting data strobe

Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets

Timing and control for deinterlacing and enhancement of non-deterministically arriving interlaced video data

Flat-panel display controller with improved dithering and frame rate control

Hardware assist for YUV data format conversion to software MPEG decoder

Block- and band-oriented traversal in three-dimensional triangle rendering

Transformerless data access arrangement

Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity

Processor having multiple datapath instances

Programmable delay timing calibrator for high speed data interface

AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip

Apparatus, systems and methods for controlling data overlay in multimedia data processing and display systems using mask techniques

Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer

Decompression of MPEG compressed data in a computer system

System and method for performing blending using an over sampling buffer

Virtual address access to tiled surfaces

Edge-triggered scan flip-flop and one-pass scan synthesis methodology

Vertically stackable integrated circuit

Multi-function controller and method for a computer graphics display system

Multiplier with selectable booth encoders for performing 3D graphics interpolations with two multiplies in a single pass through the multiplier

System and method for the mixing of graphics and video signals

Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register

Sigma-delta digital-to-analog conversion system and process through reconstruction and resampling

System and method for copy protecting computer graphics

Hybrid circuit model simulator for accurate timing and noise analysis

Adaptive dynamic aperture correction

Opposing directional fill calculators in a graphics processor

Method and apparatus for shortening display list instructions

Output buffer circuit and method that compensate for operating conditions and manufacturing processes

Voltage level shift system and method

Dual image computer display controller

Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation

Index and storage system for data provided in the vertical blanking interval

Variable band size compositing buffer method and apparatus

Dual-instruction-set CPU having shared register for storing data before switching to the alternate instruction set

Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes

Method and apparatus for correction of video tearing associated with a video and graphics shared frame buffer, as displayed on a graphics monitor

Voltage tolerant buffer

Fast adder/subtractor for signed floating point numbers

Efficient routing from multiple sources to embedded DRAM and other large circuit blocks

System and method for simultaneous flicker filtering and overscan compensation

Method and apparatus for adjusting graphics processing procedures based on a selectable speed/quality gauge

Correction of flicker associated with noninterlaced-to-interlaced video conversion

Controller for processing different pixel data types stored in the same display memory by use of tag bits

Register set reordering for a graphics processor based upon the type of primitive to be rendered

Open high speed bus for microcomputer system