Inventor · disambiguated record
Mark Hoinkis
Also filed as: HOINKIS MARK · HOINKIS MARK D
29 granted patents·6 pending applications·928 citations·filing 1996–2014
97Inventor score
Files withIBM12INFINEON TECHNOLOGIES AG9INFINEON TECHNOLOGIES CORP5APPLIED MATERIALS INC4HOINKIS MARK1
Top patents by PatentIndex Score
35 records- 0198US9493879B2Selective sputtering for pattern transferAPPLIED MATERIALS INC·Filed 2013·Granted Nov 15, 2016·132 cites·15 claims
- 0298US9114438B2Copper residue chamber cleanAPPLIED MATERIALS INC·Filed 2013·Granted Aug 25, 2015·184 cites·13 claims
- 0392US8871107B2Subtractive plasma etching of a blanket layer of metal or metal alloyIBM·Filed 2013·Granted Oct 28, 2014·13 cites·24 claims
- 0489US7241681B2Bilayered metal hardmasks for use in dual damascene etch schemesIBM·Filed 2006·Granted Jul 10, 2007·13 cites·8 claims
- 0588US6218298B1Tungsten-filled deep trenchesINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Apr 17, 2001·73 cites·1 claims
- 0687US6221757B1Method of making a microelectronic structureINFINEON TECHNOLOGIES AG·Filed 1999·Granted Apr 24, 2001·100 cites·5 claims
- 0787US6146517AIntegrated circuits with copper metallization for interconnectionsINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Nov 14, 2000·71 cites·16 claims
- 0884US9484220B2Sputter etch processing for heavy metal patterning in integrated circuitsIBM·Filed 2013·Granted Nov 1, 2016·6 cites·24 claims
- 0983US7060619B2Reduction of the shear stress in copper via's in organic interlayer dielectric materialINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jun 13, 2006·39 cites·16 claims
- 1083US6218279B1Vertical fuse and method of fabricationINFINEON TECHNOLOGIES CORP·Filed 2000·Granted Apr 17, 2001·31 cites·24 claims
- 1182US9171796B1Sidewall image transfer for heavy metal patterning in integrated circuitsIBM·Filed 2014·Granted Oct 27, 2015·5 cites·19 claims
- 1282US5872694AMethod and apparatus for determining wafer warpage for optimized electrostatic chuck clamping voltageSIEMENS AG·Filed 1997·Granted Feb 16, 1999·64 cites·24 claims
- 1380US7122462B2Back end interconnect with a shaped interfaceINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 17, 2006·25 cites·5 claims
- 1476US7052621B2Bilayered metal hardmasks for use in Dual Damascene etch schemesIBM·Filed 2003·Granted May 30, 2006·15 cites·15 claims
- 1573US7241696B2Method for depositing a metal layer on a semiconductor interconnect structure having a capping layerINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jul 10, 2007·20 cites·19 claims
- 1673US6242789B1Vertical fuse and method of fabricationINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Jun 5, 2001·38 cites·16 claims
- 1770US6539625B2Chromium adhesion layer for copper vias in low-k technologyIBM·Filed 2001·Granted Apr 1, 2003·17 cites·9 claims
- 1870US6383929B1Copper vias in low-k technologyIBM·Filed 2001·Granted May 7, 2002·17 cites·5 claims
- 1966US6864171B1Via density rulesINFINEON TECHNOLOGIES AG·Filed 2003·Granted Mar 8, 2005·13 cites·15 claims
- 2059US9960052B2Methods for etching a metal layer to form an interconnection structure for semiconductor applicationsAPPLIED MATERIALS INC·Filed 2014·Granted May 1, 2018·1 cites·16 claims
- 2158US7091612B2Dual damascene structure and methodIBM·Filed 2003·Granted Aug 15, 2006·8 cites·26 claims
- 2252US7786007B2Method and apparatus of stress relief in semiconductor structuresINFINEON TECHNOLOGIES AG·Filed 2008·Granted Aug 31, 2010·0 cites·18 claims
- 2352US6057236ACVD/PVD method of filling structures using discontinuous CVD AL linerIBM·Filed 1998·Granted May 2, 2000·17 cites·13 claims
- 2449US7494915B2Back end interconnect with a shaped interfaceIBM·Filed 2006·Granted Feb 24, 2009·0 cites·7 claims
- 2549US6960835B2Stress-relief layer for semiconductor applicationsUNITED MICROELECTRONICS CO·Filed 2003·Granted Nov 1, 2005·4 cites·27 claims
- 2649US6870263B1Device interconnectionINFINEON TECHNOLOGIES AG·Filed 1998·Granted Mar 22, 2005·15 cites·17 claims
- 2747US7368804B2Method and apparatus of stress relief in semiconductor structuresINFINEON TECHNOLOGIES AG·Filed 2003·Granted May 6, 2008·2 cites·19 claims
- 2844US2005221610A1Method and apparatus of stress relief in semiconductor structuresHOINKIS MARK·Filed 2005·Application pending·0 cites
- 2942US2007059922A1Post-etch removal of fluorocarbon-based residues from a hybrid dielectric structureIBM·Filed 2005·Application pending·0 cites
- 3040US7001835B2Crystallographic modification of hard mask propertiesINFINEON TECHNOLOGIES AG·Filed 2003·Granted Feb 21, 2006·0 cites·10 claims
- 3139US2005208742A1Oxidized tantalum nitride as an improved hardmask in dual-damascene processingIBM·Filed 2004·Application pending·0 cites
- 3239US2005116342A1Device interconnectionFiled 2004·Application pending·0 cites
- 3336US5989633AProcess for overcoming CVD aluminum selectivity loss with warm PVD aluminumAPPLIED MATERIALS INC·Filed 1996·Granted Nov 23, 1999·5 cites·15 claims
- 3436US2004058526A1Via liner integration to avoid resistance shift and resist mechanical stressINFINEON TECHNOLOGIES CORP·Filed 2002·Application pending·0 cites
- 3535US2003042580A1Elimination of via-resistance-shift by increasing via size at a last levelFiled 2001·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Mark Hoinkis files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →