US2005116342A1PendingUtilityA1

Device interconnection

Priority: Mar 31, 1998Filed: Dec 28, 2004Published: Jun 2, 2005
Est. expiryMar 31, 2018(expired)· nominal 20-yr term from priority
H10W 20/425H10W 20/084H10W 20/045H10W 20/40H10W 20/037H10W 20/033H10D 84/01
39
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Claims

Abstract

A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit comprising: 
 a dielectric layer formed over a substrate;    a recess in the dielectric layer, the recess comprising a bottom surface and first and second sidewalls;    a conductor located in the recess, the conductor comprising a conductive material having a random grain orientation; and    a liner layer lining the bottom surface and first and second sidewalls of the recess and contacting the conductor, wherein first liner layer imparts the random grain orientation in the conductive material of the first conductor.    
   
   
       2 . The integrated circuit of  claim 1  and further comprising a second liner overlying a top surface of the conductor such that liner layer and the second liner layer fully encapsulate the conductor.  
   
   
       3 . The integrated circuit of  claim 1  wherein the liner layer imparts the random grain orientation in the conductive material of the second conductor in such a ways so as to improve electromigration lifetime of the conductor.  
   
   
       4 . The integrated circuit of  claim 1  wherein the recess comprises a damascene structure.  
   
   
       5 . The integrated circuit of  claim 4  and further comprising: 
 a second dielectric layer over the dielectric layer and the conductor;    a second damascene structure in the second dielectric layer, the second damascene structure comprising a bottom surface and second sidewalls;    a second conductor located in the damascene structure and being electrically connected to the first conductor, the second conductor comprising a conductive material having a random grain orientation;    a second liner layer lining the bottom surface and sidewalls of the second damascene structure, wherein the second liner layer imparts the random grain orientation in the conductive material of the second conductor.    
   
   
       6 . The integrated circuit of  claim 1  wherein the liner layer comprises a material having a random grain orientation.  
   
   
       7 . The integrated circuit of  claim 1  wherein the liner layer comprises a material of an amorphous character.  
   
   
       8 . The integrated circuit of  claim 1  wherein the liner layer comprises at least one material selected from the group consisting essentially of titanium nitride, tantalum and tantalum nitride.  
   
   
       9 . The integrated circuit of  claim 1  wherein the liner layer comprises a layer of titanium nitride, the layer being between about 10 Angstroms and about 1000 Angstroms thick.  
   
   
       10 . The integrated circuit of  claim 9  wherein the layer of titanium nitride is about 50 Angstroms thick.  
   
   
       11 . The integrated circuit of  claim 1  and further comprising a subliner between the liner layer and the dielectric layer.  
   
   
       12 . The integrated circuit of  claim 1  wherein the subliner comprises titanium.  
   
   
       13 . The integrated circuit of  claim 12  wherein the subliner comprise a layer of titanium that is between about 10 Angstroms and about 300 Angstroms thick.  
   
   
       14 . The integrated circuit of  claim 1  wherein the second conductor comprises at least one material selected from the group consisting of aluminum, copper and tungsten.  
   
   
       15 . The integrated circuit of  claim 1  wherein the conductor has a thickness of about 3700 Angstroms.  
   
   
       16 . The integrated circuit of  claim 1  wherein the conductor comprises aluminum.  
   
   
       17 . The integrated circuit of  claim 16  wherein the liner comprises titanium nitride.  
   
   
       18 . The integrated circuit of  claim 17  and further comprising a subliner located between the liner layer and the dielectric layer, the subliner comprising titanium.  
   
   
       19 . The integrated circuit of  claim 1  wherein the conductor comprises copper.  
   
   
       20 . The integrated circuit of  claim 19  wherein the liner comprises tantulum nitride.

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