Inventor · disambiguated record
Ching-Hua Chu
Also filed as: CHU CHING-HUA
12 granted patents·4 pending applications·170 citations·filing 1993–2024
89Inventor score
Files withCHROMA ATE INC4INTEL CORP4TAIWAN SEMICONDUCTOR MFG CO LTD3LIN MEI-HSUAN2TAIWAN SEMICONDUCTOR MFG2
Top patents by PatentIndex Score
16 records- 0189US5517136AOpportunistic time-borrowing domino logicINTEL CORP·Filed 1995·Granted May 14, 1996·73 cites·34 claims
- 0287US9842774B1Through substrate via structure for noise reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 12, 2017·7 cites·20 claims
- 0370US8994097B2MOS devices having non-uniform stressor dopingLIN MEI-HSUAN·Filed 2012·Granted Mar 31, 2015·2 cites·20 claims
- 0469US9978604B2Salicide formation using a cap layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 22, 2018·1 cites·19 claims
- 0558US5479641AMethod and apparatus for overlapped timing of cache operations including reading and writing with parity checkingINTEL CORP·Filed 1993·Granted Dec 26, 1995·35 cites·14 claims
- 0657US9841487B2Calibration board for calibrating signal delays of test channels in an automatic test equipment and timing calibration method thereofCHROMA ATE INC·Filed 2015·Granted Dec 12, 2017·1 cites·8 claims
- 0755US2018261461A1Salicide formation using a cap layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Application pending·0 cites
- 0853US5737569AMultiport high speed memory having contention arbitration capability without standby delayINTEL CORP·Filed 1996·Granted Apr 7, 1998·29 cites·2 claims
- 0952US9343318B2Salicide formation using a cap layerLIN MEI-HSUAN·Filed 2012·Granted May 17, 2016·0 cites·5 claims
- 1049US5450565ACircuit and method for selecting a set in a set associative cacheINTEL CORP·Filed 1993·Granted Sep 12, 1995·22 cites·11 claims
- 1148US10802070B2Testing device and testing method with spike protectionCHROMA ATE INC·Filed 2018·Granted Oct 13, 2020·0 cites·20 claims
- 1248US9209270B2MOS devices having non-uniform stressor dopingTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Dec 8, 2015·0 cites·19 claims
- 1347US2025217068A1Method for writing test parameters to board memoriesLEE PING HUANG·Filed 2024·Application pending·0 cites
- 1440US2007087544A1Method for forming improved bump structureTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 1535US9647650B2Clock generating deviceCHROMA ATE INC·Filed 2015·Granted May 9, 2017·0 cites·7 claims
- 1633US2017168100A1Pulse generating apparatus and calibrating method thereofCHROMA ATE INC·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →