Salicide formation using a cap layer

Abstract

A semiconductor device includes a substrate having a source feature and a drain feature therein configured to enhance charge mobility, a gate stack directly over a portion of the source feature and a portion of the drain feature, a first salicide layer over substantially the entire source feature exposed by the gate stack, and a second salicide layer over substantially the entire drain feature exposed by the gate stack. The first salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight. The second salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate having a source feature and a drain feature therein configured to enhance charge mobility;   a gate stack directly over a portion of the source feature and a portion of the drain feature;   a first salicide layer over substantially the entire source feature exposed by the gate stack, wherein the first salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight; and   a second salicide layer over substantially the entire drain feature exposed by the gate stack, wherein the second salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first salicide layer and the second salicide layer independently comprise at least one of nickel, cobalt, titanium or platinum. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first salicide layer and the second salicide layer independently have a thickness ranging from about 120 Angstroms to about 300 Angstroms. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising electrical contacts, wherein each electrical contact of the electrical contact is connected to a corresponding one of the first salicide layer or the second salicide layer. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a gate salicide layer over a top surface of the gate stack. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the source feature and the drain feature comprise silicon germanium. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the source feature and the drain feature are substantially free of silicon. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the source feature and the drain feature are configured to increase hole mobility. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the gate stack comprises:
 a gate electrode; and   spacers adjacent to sidewalls of the gate electrode, wherein the spacers are between the first salicide layer and the gate electrode.   
     
     
         10 . A semiconductor device comprising:
 a substrate having a source feature and a drain feature therein, wherein each of the source feature and the drain feature comprises a germanium-containing semiconductor material;   a gate stack directly over a portion of the source feature and a portion of the drain feature;   a first salicide layer over substantially the entire source feature exposed by the gate stack, wherein the first salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight;   a second salicide layer over substantially the entire drain feature exposed by the gate stack, wherein the second salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight; and   a gate salicide layer over a top surface of the gate stack.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the source feature and the drain feature comprise silicon germanium. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the gate stack comprises:
 a gate dielectric;   a gate electrode over the gate dielectric; and   gate spacers adjacent to sidewalls of the gate electrode and sidewalls of the gate dielectric.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the gate dielectric comprises silicon dioxide, hafnium silicate, zirconium silicate, hafnium dioxide, or zirconium dioxide. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the gate electrode comprises polysilicon. 
     
     
         15 . The semiconductor device of  claim 12 , wherein an entirety of one of the gate spacers is over the source feature. 
     
     
         16 . The semiconductor device of  claim 12 , wherein an entirety of another one of the gate spacers is over the drain feature. 
     
     
         17 . A semiconductor device comprising:
 a substrate having a source feature and a drain feature therein;   a gate stack directly over a portion of the source feature and a portion of the drain feature;   a first salicide layer over substantially the entire source feature exposed by the gate stack; and   a second salicide layer over substantially the entire drain feature exposed by the gate stack,   wherein bottoms surfaces of the first salicide layer and the second salicide layer are substantially coplanar with a top surface of the substrate.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the first salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight. 
     
     
         19 . The semiconductor device of  claim 17 , wherein the second salicide layer has a germanium concentration greater than about 0% by weight and less than about 3% by weight. 
     
     
         20 . The semiconductor device of  claim 17 , wherein the first salicide layer and the second salicide layer surround a lower portion of the gate stack.