Inventor · disambiguated record
Valerie H. Chickanosky
Also filed as: CHICKANOSKY VALERIE · CHICKANOSKY VALERIE H · CHICKANOSKY VALERIE HORNBECK
8 granted patents·2 pending applications·34 citations·filing 2002–2019
84Inventor score
Top patents by PatentIndex Score
10 records- 0176US7735031B2Method and apparatus for self identification of circuitryIBM·Filed 2007·Granted Jun 8, 2010·8 cites·17 claims
- 0274US6934103B2Read channel with automatic servo track writerHITACHI GLOBAL STORAGE TECH·Filed 2002·Granted Aug 23, 2005·10 cites·23 claims
- 0370US8612813B2Circuit and method for efficient memory repairIBM·Filed 2013·Granted Dec 17, 2013·3 cites·14 claims
- 0466US10014074B2Failure analysis and repair register sharing for memory BISTGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 3, 2018·2 cites·20 claims
- 0562US6937414B2Method and apparatus for fine position adjustment using phase in a servo track writer for disk drivesHITACHI GLOBAL STORAGE TECH·Filed 2002·Granted Aug 30, 2005·5 cites·20 claims
- 0661US7757141B2Automatically extensible addressing for shared array built-in self-test (ABIST) circuitryIBM·Filed 2008·Granted Jul 13, 2010·3 cites·7 claims
- 0756US10950325B2Memory built-in self test error correcting code (MBIST ECC) for low voltage memoriesMARVELL ASIA PTE LTD·Filed 2019·Granted Mar 16, 2021·1 cites·16 claims
- 0854US8381052B2Circuit and method for efficient memory repairIBM·Filed 2009·Granted Feb 19, 2013·2 cites·21 claims
- 0937US2011029827A1Method, apparatus, and design structure for built-in self-testIBM·Filed 2009·Application pending·0 cites
- 1034US2008046789A1Apparatus and method for testing memory devices and circuits in integrated circuitsARSOVSKI IGOR·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →