Inventor · disambiguated record
Hsien-Ching Lo
Also filed as: LO HSIEN-CHING
31 granted patents·3 pending applications·182 citations·filing 2010–2019
96Inventor score
Files withGLOBALFOUNDRIES INC28TAIWAN SEMICONDUCTOR MFG2CHENG CHUN-FAI1FUNG KA-HING1GLOBALFOUNDRIES US INC1
Top patents by PatentIndex Score
34 records- 0198US10163635B1Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related methodGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 25, 2018·26 cites·13 claims
- 0297US10249538B1Method of forming vertical field effect transistors with different gate lengths and a resulting structureGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 2, 2019·22 cites·19 claims
- 0396US9947769B1Multiple-layer spacers for field-effect transistorsGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 17, 2018·14 cites·9 claims
- 0495US9887094B1Methods of forming EPI semiconductor material on the source/drain regions of a FinFET deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 6, 2018·14 cites·12 claims
- 0595US9419101B1Multi-layer spacer used in finFETGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 16, 2016·20 cites·20 claims
- 0695US8502316B2Self-aligned two-step STI formation through dummy poly removalFUNG KA-HING·Filed 2010·Granted Aug 6, 2013·23 cites·20 claims
- 0793US10559656B2Wrap-all-around contact for nanosheet-FET and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 11, 2020·8 cites·9 claims
- 0893US10388652B2Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 20, 2019·10 cites·14 claims
- 0993US10068810B1Multiple Fin heights with dielectric isolationGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 4, 2018·9 cites·10 claims
- 1091US10050125B1Vertical-transport field-effect transistors with an etched-through source/drain cavityGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 14, 2018·6 cites·17 claims
- 1187US10553707B1FinFETs having gates parallel to finsGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 4, 2020·5 cites·20 claims
- 1283US10068902B1Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 4, 2018·4 cites·4 claims
- 1379US10957578B2Single diffusion break device for FDSOIGLOBALFOUNDRIES US INC·Filed 2018·Granted Mar 23, 2021·2 cites·20 claims
- 1477US9847225B2Semiconductor device and method of manufacturing the sameCHENG CHUN-FAI·Filed 2011·Granted Dec 19, 2017·4 cites·21 claims
- 1572US10410929B2Multiple gate length device with self-aligned top junctionGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 10, 2019·1 cites·19 claims
- 1672US10211317B1Vertical-transport field-effect transistors with an etched-through source/drain cavityGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 19, 2019·1 cites·20 claims
- 1771US8535998B2Method for fabricating a gate structureHING FUNG KA·Filed 2010·Granted Sep 17, 2013·4 cites·19 claims
- 1871US8368147B2Strained semiconductor device with recessed channelTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Feb 5, 2013·3 cites·12 claims
- 1970US10297675B1Dual-curvature cavity for epitaxial semiconductor growthGLOBALFOUNDRIES INC·Filed 2017·Granted May 21, 2019·1 cites·13 claims
- 2069US10262903B2Boundary spacer structure and integrationGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 16, 2019·1 cites·15 claims
- 2169US8952459B2Gate structure having lightly doped regionTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Feb 10, 2015·2 cites·20 claims
- 2267US10276689B2Method of forming a vertical field effect transistor (VFET) and a VFET structureGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 30, 2019·1 cites·11 claims
- 2367US10121868B1Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 6, 2018·1 cites·20 claims
- 2454US10431665B2Multiple-layer spacers for field-effect transistorsGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 1, 2019·0 cites·20 claims
- 2551US2019181243A1Dual-curvature cavity for epitaxial semiconductor growthGLOBALFOUNDRIES INC·Filed 2019·Application pending·0 cites
- 2650US10714577B2Etch stop layer for use in forming contacts that extend to multiple depthsGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·0 cites·20 claims
- 2750US10636894B2Fin-type transistors with spacers on the gatesGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 28, 2020·0 cites·19 claims
- 2849US10546775B1Field-effect transistors with improved dielectric gap fillGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 28, 2020·0 cites·19 claims
- 2948US10700173B2FinFET device with a wrap-around silicide source/drain contact structureGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 30, 2020·0 cites·16 claims
- 3043US10355104B2Single-curvature cavity for semiconductor epitaxyGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 16, 2019·0 cites·14 claims
- 3143US2020020770A1Composite spacers for tailoring the shape of the source and drain regions of a field-effect transistorGLOBALFOUNDRIES INC·Filed 2018·Application pending·0 cites
- 3239US10164010B1Finfet diffusion break having protective liner in fin insulatorGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 25, 2018·0 cites·20 claims
- 3337US10461155B2Epitaxial region for embedded source/drain region having uniform thicknessGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 29, 2019·0 cites·10 claims
- 3432US2018190792A1Method of forming semiconductor structure and resulting structureGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →