Inventor · disambiguated record
Deepak D. Sherlekar
Also filed as: SHERLEKAR DEEPAK · SHERLEKAR DEEPAK D · SHERLEKAR DEEPAK DATTATRAYA
36 granted patents·3 pending applications·707 citations·filing 1996–2023
98Inventor score
Top patents by PatentIndex Score
39 records- 0197US8924908B2FinFET cell architecture with power tracesSYNOPSYS INC·Filed 2013·Granted Dec 30, 2014·23 cites·22 claims
- 0297US8723268B2N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitchMOROZ VICTOR·Filed 2012·Granted May 13, 2014·26 cites·33 claims
- 0397US8595661B2N-channel and p-channel finFET cell architectureKAWA JAMIL·Filed 2011·Granted Nov 26, 2013·36 cites·29 claims
- 0497US8561003B2N-channel and P-channel finFET cell architecture with inter-block insulatorKAWA JAMIL·Filed 2011·Granted Oct 15, 2013·43 cites·37 claims
- 0597US6617621B1Gate array architecture using elevated metal levels for customizationVIRAGE LOGIC CORP·Filed 2000·Granted Sep 9, 2003·229 cites·53 claims
- 0696US8513978B2Power routing in standard cell designsSHERLEKAR DEEPAK D·Filed 2012·Granted Aug 20, 2013·39 cites·24 claims
- 0795US9048121B2FinFET cell architecture with insulator structureSYNOPSYS INC·Filed 2013·Granted Jun 2, 2015·16 cites·13 claims
- 0893US9691764B2FinFET cell architecture with power tracesSYNOPSYS INC·Filed 2015·Granted Jun 27, 2017·7 cites·18 claims
- 0992US9257429B2N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitchSYNOPSYS INC·Filed 2015·Granted Feb 9, 2016·7 cites·36 claims
- 1092US9076673B2FinFET cell architecture with power tracesSYNOPSYS INC·Filed 2014·Granted Jul 7, 2015·8 cites·23 claims
- 1192US8987828B2N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitchSYNOPSYS INC·Filed 2014·Granted Mar 24, 2015·10 cites·11 claims
- 1291US8612914B2Pin routing in standard cellsSHERLEKAR DEEPAK D·Filed 2011·Granted Dec 17, 2013·29 cites·24 claims
- 1390US8742464B2Power routing in standard cellsSHERLEKAR DEEPAK D·Filed 2011·Granted Jun 3, 2014·19 cites·12 claims
- 1489US7069522B1Various methods and apparatuses to preserve a logic state for a volatile latch circuitVIRAGE LOGIC CORP·Filed 2004·Granted Jun 27, 2006·46 cites·27 claims
- 1588US8941150B2Power routing in standard cellsSYNOPSYS INC·Filed 2014·Granted Jan 27, 2015·11 cites·20 claims
- 1688US7989849B2Apparatuses and methods for efficient power rail structures for cell librariesSYNOPSYS INC·Filed 2007·Granted Aug 2, 2011·51 cites·20 claims
- 1785US11847396B1Integrated circuit design using multi-bit combinational cellsSYNOPSYS INC·Filed 2021·Granted Dec 19, 2023·3 cites·20 claims
- 1885US11403454B2Placement and simulation of cell in proximity to cell with diffusion breakSYNOPSYS INC·Filed 2020·Granted Aug 2, 2022·2 cites·14 claims
- 1985US7603634B2Various methods and apparatuses to preserve a logic state for a volatile latch circuitVIRAGE LOGIC CORP·Filed 2006·Granted Oct 13, 2009·15 cites·19 claims
- 2084US11790150B2Placement and simulation of cell in proximity to cell with diffusion breakSYNOPSYS INC·Filed 2022·Granted Oct 17, 2023·1 cites·20 claims
- 2184US7219324B1Various methods and apparatuses to route multiple power rails to a cellVIRAGE LOGIC CORP·Filed 2004·Granted May 15, 2007·35 cites·21 claims
- 2280US8631374B2Cell architecture for increasing transistor sizeSHERLEKAR DEEPAK D·Filed 2012·Granted Jan 14, 2014·6 cites·25 claims
- 2378US10990722B2FinFET cell architecture with insulator structureSYNOPSYS INC·Filed 2015·Granted Apr 27, 2021·2 cites·9 claims
- 2476US8392862B1Structures and methods for optimizing power consumption in an integrated chip designSIGUENZA OSCAR·Filed 2007·Granted Mar 5, 2013·13 cites·16 claims
- 2572US12079558B2On-the-fly multi-bit flip flop generationSYNOPSYS INC·Filed 2023·Granted Sep 3, 2024·0 cites·20 claims
- 2671US10205440B2Retention flip-flop circuits for low power applicationsSYNOPSYS INC·Filed 2017·Granted Feb 12, 2019·3 cites·19 claims
- 2764US11681848B2On-the-fly multi-bit flip flop generationSYNOPSYS INC·Filed 2021·Granted Jun 20, 2023·0 cites·16 claims
- 2862US8132142B2Various methods and apparatuses to route multiple power rails to a cellSHERLEKAR DEEPAK D·Filed 2007·Granted Mar 6, 2012·2 cites·20 claims
- 2957US12231125B1Power efficient retention flip flop circuitSYNOPSYS INC·Filed 2023·Granted Feb 18, 2025·0 cites·20 claims
- 3055US12086523B2Adaptive row patterns for custom-tiled placement fabrics for mixed height cell librariesSYNOPSYS INC·Filed 2021·Granted Sep 10, 2024·0 cites·18 claims
- 3154US2015303196A1Finfet cell architecture with power tracesSYNOPSYS INC·Filed 2015·Application pending·0 cites
- 3253US12248744B2Poly-bit cellsSYNOPSYS INC·Filed 2021·Granted Mar 11, 2025·0 cites·20 claims
- 3352US11657205B2Construction, modeling, and mapping of multi-output cellsSYNOPSYS INC·Filed 2021·Granted May 23, 2023·0 cites·20 claims
- 3451US11837280B1CFET architecture for balancing logic library and SRAM bitcellSYNOPSYS INC·Filed 2020·Granted Dec 5, 2023·0 cites·20 claims
- 3551US5943243AMethod and system for removing hardware design overlapIBM·Filed 1996·Granted Aug 24, 1999·25 cites·24 claims
- 3651US2025004521A1Timing and power modeling in flexmbff compilersSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 3747US11416661B2Automatic derivation of integrated circuit cell mapping rules in an engineering change order flowSYNOPSYS INC·Filed 2020·Granted Aug 16, 2022·0 cites·19 claims
- 3847US2013200945A1Structures and methods for optimizing power consumption in an integrated chip designSYNOPSYS INC·Filed 2013·Application pending·0 cites
- 3944US11328109B2Refining multi-bit flip flops mapping without explicit de-banking and re-bankingSYNOPSYS INC·Filed 2020·Granted May 10, 2022·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →