Structures and methods for optimizing power consumption in an integrated chip design

Abstract

Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state.

What is claimed is: 
     
         1 . A non-transitory computer-readable storage medium storing a representation of a power distribution structure surrounding a logic block in an integrated circuit (IC), the representation comprising:
 at least one enable cell connected to an enable rail configured to transmit a control signal;   a first power gating cell comprising a first gating element configured to switch on or off a path between a power rail and at least one cell in the logic block according to the control signal received via the enable rail;   a second gating cell comprising a second gating element configured to switch on or off a path between the power rail and the at least one cell, the second gating element having different voltage threshold characteristics or a different channel length compared to the first power gating element and derived from a same cell library; and   at least one filler cell comprising a gating element having a gate terminal connected to receive the control signal.   
     
     
         2 . The computer-readable storage medium of  claim 1 , wherein a number of enable cells, a number of power gating cells and a number of filler cell in the power distribution structure are selected to configure a current profile or voltage profile at a node in the logic block. 
     
     
         3 . The computer-readable storage medium of  claim 2 , wherein the voltage threshold characteristics or the channel lengths of the first and second gating elements are selected to configure the current profile or the voltage profile at the node. 
     
     
         4 . The computer-readable storage medium of  claim 1 , wherein the first gating element and the second gating element are P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or N-type MOSFETs with gates connected to the enable rail. 
     
     
         5 . The computer-readable storage medium of  claim 1 , wherein the power distribution structure further includes at least one corner cell configured to connect power rails to cells at different portions of the power distribution structure. 
     
     
         6 . The computer-readable storage medium of  claim 5 , wherein the at least one corner cell is configured to connect a power rail extending along a first side of the power distribution structure and another power rail extending along a second side of the power distribution structure perpendicular to the first side. 
     
     
         7 . The computer-readable storage medium of  claim 1 , wherein the at least one enable cell and power gating cells are separated by at least one cell in the power distribution structure. 
     
     
         8 . The computer-readable storage medium of  claim 1 , wherein the power rail is formed as a metal layer lower in height than another metal layer for routing power to the IC. 
     
     
         9 . The computer-readable storage medium of  claim 1 , wherein the at least one enable cell is further configured to propagate an acknowledge signal to a plurality of cells in the power distribution structure. 
     
     
         10 . A power distribution structure surrounding a logic block in an integrated circuit (IC), the power distribution structure comprising:
 at least one enable cell connected to an enable rail configured to transmit a control signal;   a first power gating cell comprising a first gating element configured to switch on or off a path between a power rail and at least one cell in the logic block according to the control signal received via the enable rail;   a second gating cell comprising a second gating element configured to switch on or off a path between the power rail and the at least one cell, the second gating element having different voltage threshold characteristics or a different channel length compared to the first power gating element and derived from a same cell library; and   at least one filler cell comprising a gating element having a gate terminal connected to receive the control signal.   
     
     
         11 . The power distribution structure of  claim 10 , wherein a number of enable cells, a number of power gating cells and a number of filler cell in the power distribution structure are selected to configure a current profile or voltage profile at a node in the logic block. 
     
     
         12 . The power distribution structure of  claim 11 , wherein the voltage threshold characteristics or the channel lengths of the first and second gating elements are selected to configure the current profile or the voltage profile at the node. 
     
     
         13 . The power distribution structure of  claim 10 , wherein the first gating element and the second gating element are P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or N-type MOSFETs with gates connected to the enable rail. 
     
     
         14 . The power distribution structure of  claim 10 , wherein the power distribution structure further includes at least one corner cell configured to connect power rails to cells at different portions of the power distribution structure. 
     
     
         15 . The power distribution structure of  claim 14 , wherein the at least one corner cell is configured to connect a power rail extending along a first side of the power distribution structure and another power rail extending along a second side of the power distribution structure perpendicular to the first side. 
     
     
         16 . The power distribution structure of  claim 10 , wherein the at least one enable cell and power gating cells are separated by at least one cell in the power distribution structure. 
     
     
         17 . A method of designing a power distribution structure surrounding a logic block in an integrated chip (IC), comprising:
 receiving a configuration the logic block in the IC;   receiving configuration of a power distribution structure, the configuration defining:
 at least one enable cell connected to an enable rail configured to transmit a control signal, 
 a first power gating cell comprising a first gating element configured to switch on or off a path between a power rail and at least one cell in the logic block according to the control signal received via the enable rail, 
 a second gating cell comprising a second gating element configured to switch on or off a path between the power rail and the at least one cell, the second gating element having different voltage threshold characteristics or a different channel length compared to the first power gating element and derived from a same cell library, and 
 at least one filler cell comprising a gating element having a gate terminal connected to receive the control signal; and 
   placing the power distribution structure to surround the logic block and connect to at least a cell in the logic block.   
     
     
         18 . The method of  claim 17 , further comprising determining a number of enable cells, a number of the power gating cells and a number of the filler cells and the voltage threshold characteristics or channel lengths of the at least two gating elements to configure a current profile or voltage profile at a node in the logic block to generate a first design of the IC. 
     
     
         19 . The method of  claim 17 , further comprising changing the number of power gating cells and the number of filler cells by connecting one or more power gating elements of a subset of the at least one filler cell to the power rail or removing connection of the first gating element or the second gating element based on a measurement taken from an IC fabricated using the first design. 
     
     
         20 . The method of  claim 19 , further comprising determining the voltage threshold characteristics or the channel lengths of the first and second gating elements to configure the current profile or the voltage profile at the node.