Finfet cell architecture with power traces

Abstract

A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

1 . An integrated circuit, comprising:
 a substrate;   a set of semiconductor fins in a region of the substrate, including outer fins on opposing outside edges of the set;   a plurality of gate traces overlying the set;   a patterned conductor layer overlying the set, and including a first patterned conductor connected to source/drain regions in a first subset of the fins, and a second patterned conductor over the set of semiconductor fins connected to source/drain regions in a second subset of the fins, where the first and second subsets have different numbers of members.