Inventor · disambiguated record
Anurag Jindal
Also filed as: JINDAL ANURAG
34 granted patents·10 pending applications·116 citations·filing 2001–2025
96Inventor score
Files withMICRON TECHNOLOGY INC17JINDAL ANURAG7NXP USA INC4FREESCALE SEMICONDUCTOR INC3NYACOL NANO TECHNOLOGIES INC3
Top patents by PatentIndex Score
44 records- 0192US9568551B1Scan wrapper circuit for integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Feb 14, 2017·12 cites·12 claims
- 0290US9766289B2LBIST debug controllerFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Sep 19, 2017·9 cites·7 claims
- 0390US9599672B2Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereofFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Mar 21, 2017·22 cites·18 claims
- 0489US9297855B1Integrated circuit with increased fault coverageJINDAL ANURAG·Filed 2014·Granted Mar 29, 2016·18 cites·19 claims
- 0585US8841952B1Data retention flip-flopSINGH NITIN·Filed 2013·Granted Sep 23, 2014·9 cites·19 claims
- 0684US9773807B1Conductive components and memory assembliesMICRON TECHNOLOGY INC·Filed 2017·Granted Sep 26, 2017·4 cites·26 claims
- 0784US9754825B2Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methodsMICRON TECHNOLOGY INC·Filed 2015·Granted Sep 5, 2017·3 cites·19 claims
- 0884US9099442B2Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methodsMICRON TECHNOLOGY INC·Filed 2013·Granted Aug 4, 2015·4 cites·21 claims
- 0981US9213063B2Reset generation circuit for scan mode exitJINDAL ANURAG·Filed 2014·Granted Dec 15, 2015·4 cites·13 claims
- 1081US9034752B2Methods of exposing conductive vias of semiconductor devices and associated structuresLI HONGQI·Filed 2013·Granted May 19, 2015·4 cites·26 claims
- 1179US9298572B2Built-in self test (BIST) with clock controlAHMED NISAR·Filed 2013·Granted Mar 29, 2016·5 cites·20 claims
- 1279US2025191972A1Methods of exposing conductive vias of semiconductor devicesMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 1376US11144677B2Method and apparatus for digital only secure test mode entryNXP USA INC·Filed 2019·Granted Oct 12, 2021·3 cites·21 claims
- 1475US10546777B2Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methodsMICRON TECHNOLOGY INC·Filed 2018·Granted Jan 28, 2020·1 cites·25 claims
- 1575US9922875B2Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methodsMICRON TECHNOLOGY INC·Filed 2017·Granted Mar 20, 2018·1 cites·27 claims
- 1675US8872252B2Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tierJINDAL ANURAG·Filed 2011·Granted Oct 28, 2014·3 cites·13 claims
- 1773US12237217B2Methods of exposing conductive Vias of semiconductor devices and related semiconductor devicesMICRON TECHNOLOGY INC·Filed 2021·Granted Feb 25, 2025·0 cites·15 claims
- 1872US8956974B2Devices, systems, and methods related to planarizing semiconductor devices after forming openingsHUANG WAYNE H·Filed 2012·Granted Feb 17, 2015·3 cites·27 claims
- 1971US11011420B2Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methodsMICRON TECHNOLOGY INC·Filed 2020·Granted May 18, 2021·0 cites·22 claims
- 2070US9285424B2Method and system for logic built-in self-testSINGH NITIN·Filed 2014·Granted Mar 15, 2016·2 cites·12 claims
- 2169US8911558B2Post-tungsten CMP cleaning solution and method of using the sameLI HONGQI·Filed 2011·Granted Dec 16, 2014·2 cites·7 claims
- 2268US10014319B1Conductive components and memory assembliesMICRON TECHNOLOGY INC·Filed 2017·Granted Jul 3, 2018·1 cites·23 claims
- 2367US9599673B2Structural testing of integrated circuitsJINDAL ANURAG·Filed 2014·Granted Mar 21, 2017·2 cites·8 claims
- 2463US9627295B2Devices, systems and methods for manufacturing through-substrate vias and front-side structuresMICRON TECHNOLOGY INC·Filed 2016·Granted Apr 18, 2017·1 cites·10 claims
- 2561US8871103B2Process of planarizing a wafer with a large step height and/or surface area featuresNANYA TECHNOLOGY CORP·Filed 2013·Granted Oct 28, 2014·1 cites·2 claims
- 2660US10847442B2Interconnect assemblies with through-silicon vias and stress-relief featuresMICRON TECHNOLOGY INC·Filed 2014·Granted Nov 24, 2020·1 cites·17 claims
- 2758US8580690B2Process of planarizing a wafer with a large step height and/or surface area featuresBUSCH BRETT·Filed 2011·Granted Nov 12, 2013·1 cites·17 claims
- 2855US10475810B2Conductive components and memory assembliesMICRON TECHNOLOGY INC·Filed 2018·Granted Nov 12, 2019·0 cites·27 claims
- 2953US2015044860A1Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tierMICRON TECHNOLOGY INC·Filed 2014·Application pending·0 cites
- 3051US2015145146A1Methods of exposing conductive vias of semiconductor devices and related semiconductor devicesMICRON TECHNOLOGY INC·Filed 2015·Application pending·0 cites
- 3149US9305865B2Devices, systems and methods for manufacturing through-substrate vias and front-side structuresMICRON TECHNOLOGY INC·Filed 2013·Granted Apr 5, 2016·0 cites·14 claims
- 3248US11821946B2Built in self test (BIST) for clock generation circuitryNXP USA INC·Filed 2021·Granted Nov 21, 2023·0 cites·20 claims
- 3348US11742282B2Conductive interconnectsMICRON TECHNOLOGY INC·Filed 2020·Granted Aug 29, 2023·0 cites·15 claims
- 3446US12265776B2Identifying test coverage gaps for integrated circuit designs based on node testability and physical design dataNXP USA INC·Filed 2021·Granted Apr 1, 2025·0 cites·16 claims
- 3546US2015206801A1Devices, systems, and methods related to planarizing semiconductor devices after forming openingsMICRON TECHNOLOGY INC·Filed 2015·Application pending·0 cites
- 3644US11513153B2System and method for facilitating built-in self-test of system-on-chipsNXP USA INC·Filed 2021·Granted Nov 29, 2022·0 cites·19 claims
- 3743US9330975B2Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate viasJINDAL ANURAG·Filed 2012·Granted May 3, 2016·0 cites·17 claims
- 3843US9201116B1Method of generating test patterns for detecting small delay defectsJINDAL ANURAG·Filed 2014·Granted Dec 1, 2015·0 cites·13 claims
- 3939US2012314171A1Display devices having electrolessly plated conductors and methodsJINDAL ANURAG·Filed 2011·Application pending·0 cites
- 4038US2003047710A1Chemical-mechanical polishingNYACOL NANO TECHNOLOGIES INC·Filed 2001·Application pending·0 cites
- 4138US2003092271A1Shallow trench isolation polishing using mixed abrasive slurriesNYACOL NANO TECHNOLOGIES INC·Filed 2002·Application pending·0 cites
- 4236US2012315754A1Interconnection barrier material device and methodZHU XIAOYUN·Filed 2011·Application pending·0 cites
- 4335US2015285859A1Integrated circuit with lbist sub-partitionsJAJODIA REECHA·Filed 2014·Application pending·0 cites
- 4434US2003211747A1Shallow trench isolation polishing using mixed abrasive slurriesNYACOL NANO TECHNOLOGIES INC·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →