Devices, systems, and methods related to planarizing semiconductor devices after forming openings

Abstract

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.

I/We claim: 
     
         1 . A method of manufacturing a semiconductor device, comprising:
 forming a stop layer on the semiconductor device;   forming openings in the semiconductor device, wherein individual openings have a sidewall extending through the stop layer and through at least a portion of a substrate of the semiconductor device;   forming a dielectric liner including a first portion along the sidewalls of the openings and a second portion at areas outside the openings, wherein the stop layer is generally between the dielectric liner and the substrate at the areas outside the openings;   filling the openings with a conductive material such that the conductive material has plug portions in the openings and an excess portion; and   simultaneously removing the excess portion of the conductive material and the second portion of the dielectric liner until the stop layer is exposed such that a remaining portion of the conductive material in the openings defines conductive plugs, wherein simultaneously removing includes selectively removing the dielectric liner relative to the stop layer at a selectivity greater than about 5:1.   
     
     
         2 . The method of  claim 1 , wherein simultaneously removing the excess portion of the conductive material and the second portion of the dielectric liner includes simultaneously chemically-mechanically removing the excess portion of the conductive material and the second portion of the dielectric liner. 
     
     
         3 . The method of  claim 1 , wherein the conductive plugs are through-substrate vias. 
     
     
         4 . The method of  claim 1 , further comprising—
 initially removing a part of the excess portion of the conductive material with a first removal step before simultaneously removing a remaining part of the excess portion of the conductive material and the second portion of the dielectric liner with a second removal step, and 
 annealing the conductive plugs after the first removal step and before the second removal step. 
 
     
     
         5 . The method of  claim 1 , wherein simultaneously removing the excess portion of the conductive material and the second portion of the dielectric liner includes using a slurry including ceria. 
     
     
         6 . The method of  claim 1 , wherein the second portion of the dielectric liner is not subjected to a removal process before filling the openings with the conductive material. 
     
     
         7 . The method of  claim 1 , further comprising removing a backside portion of the semiconductor device, the backside portion including a portion of the substrate and the one or more lower portions of the plug portions. 
     
     
         8 . The method of  claim 1 , wherein—
 the stop layer includes silicon nitride, and 
 the dielectric liner includes silicon dioxide. 
 
     
     
         9 . The method of  claim 1 , wherein—
 the conductive material is copper, and 
 simultaneously removing the excess portion of the conductive material and the second portion of the dielectric liner includes removing the dielectric liner relative to copper at a selectivity from about 0.5:1 to about 1.5:1. 
 
     
     
         10 . The method of  claim 1 , wherein—
 the stop layer includes a low-k dielectric material, and 
 the dielectric liner includes silicon dioxide. 
 
     
     
         11 . The method of  claim 10 , wherein the low-k dielectric material is carbon-doped silicon nitride. 
     
     
         12 . The method of  claim 1 , wherein simultaneously removing the excess portion of the conductive material and the second portion of the dielectric liner includes using a slurry including an abrasive and an oxidizing agent at concentrations selected to cause the selectivity. 
     
     
         13 . The method of  claim 12 , wherein the abrasive is ceria and the oxidizing agent is ammonium persulfate. 
     
     
         14 . The method of  claim 12 , wherein the abrasive is silicon dioxide and the oxidizing agent is ammonium persulfate. 
     
     
         15 . A method for forming through-substrate vias in a semiconductor device, comprising:
 forming openings through at least a portion of a substrate of the semiconductor device;   forming a dielectric layer including a liner portion at sidewalls of the openings and excess dielectric material at areas outside the openings;   forming a metal layer including via portions within the openings and excess metal;   simultaneously chemically-mechanically removing the excess metal and the excess dielectric material such that the via portions are electrically separated from one another at one end; and   removing at least a portion of the substrate such that opposing ends of the via portions are exposed and the via portions form through-substrate vias.   
     
     
         16 . The method of  claim 15 , wherein removing includes backgrinding. 
     
     
         17 . The method of  claim 15 , wherein—
 the metal layer includes copper, and 
 simultaneously chemically-mechanically removing the excess metal and the excess dielectric material includes removing the excess metal relative to the excess dielectric material at a selectivity from about 0.5:1 to about 1.5:1. 
 
     
     
         18 . The method of  claim 15 , wherein simultaneously chemically-mechanically removing the excess metal and the excess dielectric material includes using a slurry including ceria. 
     
     
         19 . The method of  claim 18 , wherein the slurry further includes ammonium persulfate. 
     
     
         20 . A method for forming vias in a semiconductor device, comprising:
 forming openings through at least a portion of a substrate of the semiconductor device;   forming a dielectric layer of the semiconductor device, the dielectric layer including a liner portion on sidewalls of the openings and excess dielectric material outside the openings;   forming a copper layer of the semiconductor device, the copper layer including copper vias within the openings and excess copper outside the openings; and   simultaneously chemically-mechanically removing the excess copper and the excess dielectric material using a slurry including ceria.