Inventor · disambiguated record
Lihu Rappoport
Also filed as: RAPPOPORT LIHU
45 granted patents·10 pending applications·466 citations·filing 1998–2024
97Inventor score
Top patents by PatentIndex Score
55 records- 0192US12236243B2Apparatuses and methods for speculative execution side channel mitigationINTEL CORP·Filed 2023·Granted Feb 25, 2025·2 cites·28 claims
- 0290US10579535B2Defragmented and efficient micro-operation cacheINTEL CORP·Filed 2017·Granted Mar 3, 2020·15 cites·20 claims
- 0389US6549987B1Cache structure for storing variable length dataINTEL CORP·Filed 2000·Granted Apr 15, 2003·49 cites·18 claims
- 0488US11635965B2Apparatuses and methods for speculative execution side channel mitigationINTEL CORP·Filed 2018·Granted Apr 25, 2023·5 cites·24 claims
- 0588US10915421B1Technology for dynamically tuning processor featuresINTEL CORP·Filed 2019·Granted Feb 9, 2021·4 cites·20 claims
- 0688US7757065B1Instruction segment recording schemeINTEL CORP·Filed 2000·Granted Jul 13, 2010·55 cites·19 claims
- 0786US8103831B2Efficient method and apparatus for employing a micro-op cache in a processorRAPPOPORT LIHU·Filed 2008·Granted Jan 24, 2012·20 cites·20 claims
- 0885US6601161B2Method and system for branch target prediction using path informationINTEL CORP·Filed 1998·Granted Jul 29, 2003·105 cites·24 claims
- 0982US11294809B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2018·Granted Apr 5, 2022·2 cites·7 claims
- 1082US6438673B1Correlated address predictionINTEL CORP·Filed 1999·Granted Aug 20, 2002·99 cites·18 claims
- 1181US9552169B2Apparatus and method for efficient memory renaming prediction using virtual registersINTEL CORP·Filed 2015·Granted Jan 24, 2017·4 cites·26 claims
- 1281US6631445B2Cache structure for storing variable length dataINTEL CORP·Filed 2003·Granted Oct 7, 2003·26 cites·19 claims
- 1375US10754655B2Automatic predication of hard-to-predict convergent branchesINTEL CORP·Filed 2018·Granted Aug 25, 2020·2 cites·18 claims
- 1475US9448879B2Apparatus and method for implement a multi-level memory hierarchyYIGZAW THEODROS·Filed 2011·Granted Sep 20, 2016·4 cites·24 claims
- 1575US2024296051A1Apparatuses and methods for speculative execution side channel mitigationINTEL CORP·Filed 2024·Application pending·0 cites
- 1673US12130740B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2022·Granted Oct 29, 2024·0 cites·15 claims
- 1773US10402263B2Accelerating memory fault resolution by performing fast re-fetchingINTEL CORP·Filed 2017·Granted Sep 3, 2019·1 cites·20 claims
- 1871US11656971B2Technology for dynamically tuning processor featuresINTEL CORP·Filed 2022·Granted May 23, 2023·0 cites·20 claims
- 1971US10949208B2System, apparatus and method for context-based override of history-based branch predictionsINTEL CORP·Filed 2018·Granted Mar 16, 2021·1 cites·15 claims
- 2071US8782374B2Method and apparatus for inclusion of TLB entries in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Jul 15, 2014·6 cites·20 claims
- 2171US8433850B2Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Apr 30, 2013·6 cites·20 claims
- 2269US10719355B2Criticality based port schedulingINTEL CORP·Filed 2018·Granted Jul 21, 2020·1 cites·20 claims
- 2369US8543796B2Optimizing performance of instructions based on sequence detection or information associated with the instructionsFALIK OHAD·Filed 2008·Granted Sep 24, 2013·4 cites·14 claims
- 2467US11256599B2Technology for dynamically tuning processor featuresINTEL CORP·Filed 2020·Granted Feb 22, 2022·0 cites·20 claims
- 2567US8127085B2Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Feb 28, 2012·4 cites·16 claims
- 2665US9690591B2System and method for fusing instructions queued during a time window defined by a delay counterOUZIEL IDO·Filed 2008·Granted Jun 27, 2017·4 cites·15 claims
- 2763US8935514B2Optimizing performance of instructions based on sequence detection or information associated with the instructionsINTEL CORP·Filed 2013·Granted Jan 13, 2015·1 cites·19 claims
- 2861US9348591B2Multi-level tracking of in-use state of cache linesKIM ILHYUN·Filed 2011·Granted May 24, 2016·2 cites·14 claims
- 2960US11150979B2Accelerating memory fault resolution by performing fast re-fetchingINTEL CORP·Filed 2019·Granted Oct 19, 2021·0 cites·20 claims
- 3059US11645078B2Detecting a dynamic control flow re-convergence point for conditional branches in hardwareINTEL CORP·Filed 2019·Granted May 9, 2023·0 cites·24 claims
- 3158US12417182B2De-prioritizing speculative code lines in on-chip cachesINTEL CORP·Filed 2021·Granted Sep 16, 2025·0 cites·21 claims
- 3258US6880063B2Memory cache bank predictionINTEL CORP·Filed 2004·Granted Apr 12, 2005·4 cites·15 claims
- 3355US12423075B2Code prefetch instructionINTEL CORP·Filed 2020·Granted Sep 23, 2025·0 cites·17 claims
- 3453US12468631B2Region aware delta prefetcherINTEL CORP·Filed 2021·Granted Nov 11, 2025·0 cites·25 claims
- 3552US12430135B2Device, method, and system to facilitate improved bandwidth of a branch prediction unitINTEL CORP·Filed 2021·Granted Sep 30, 2025·0 cites·20 claims
- 3652US10649783B2Multicore system for fusing instructions queued during a dynamically adjustable time windowINTEL CORP·Filed 2016·Granted May 12, 2020·0 cites·19 claims
- 3752US7802077B1Trace indexing via trace end addressesINTEL CORP·Filed 2000·Granted Sep 21, 2010·3 cites·15 claims
- 3852US2025298622A1Circuitry and methods for early fetch of call instructionsINTEL CORP·Filed 2024·Application pending·0 cites
- 3952US2025217157A1Software defined super coresINTEL CORP·Filed 2023·Application pending·0 cites
- 4050US7428627B2Method and apparatus for predicting values in a processor having a plurality of prediction modesINTEL CORP·Filed 2000·Granted Sep 23, 2008·1 cites·22 claims
- 4150US6625744B1Controlling population size of confidence assignmentsINTEL CORP·Filed 1999·Granted Sep 23, 2003·21 cites·30 claims
- 4249US10467011B2Thread pause processors, methods, systems, and instructionsINTEL CORP·Filed 2014·Granted Nov 5, 2019·0 cites·12 claims
- 4348US10095522B2Instruction and logic for register based hardware memory renamingINTEL CORP·Filed 2014·Granted Oct 9, 2018·0 cites·20 claims
- 4448US9678807B2Hybrid threadingINTEL CORP·Filed 2013·Granted Jun 13, 2017·0 cites·19 claims
- 4548US7644236B2Memory cache bank predictionINTEL CORP·Filed 2005·Granted Jan 5, 2010·0 cites·12 claims
- 4648US2021200538A1Dual write micro-op queueINTEL CORP·Filed 2019·Application pending·0 cites
- 4747US9027009B2Protecting the integrity of binary translated codeRAIKIN SHLOMO·Filed 2011·Granted May 5, 2015·0 cites·20 claims
- 4847US6694421B2Cache memory bank access predictionINTEL CORP·Filed 1999·Granted Feb 17, 2004·15 cites·5 claims
- 4946US2021200550A1Loop exit predictorINTEL CORP·Filed 2019·Application pending·0 cites
- 5045US2023195465A1Device, method and system to provide a predicted value with a sequence of micro-operationsINTEL CORP·Filed 2021·Application pending·0 cites
Showing the top 50 of 55 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →