Dual write micro-op queue

Abstract

Disclosed embodiments relate to systems and methods to dually write micro-ops to a micro-op queue. A processor includes a micro-op cache communicatively coupled, via a first write port, to a micro-op queue, and a legacy fetch and decode pipeline communicatively coupled, via a second write port, to the micro-op queue, the processor to determine whether the micro-op cache stores a thread, the thread comprising a micro-op to be written to the micro-op queue, determine whether the legacy fetch and decode pipeline stores the thread if the micro-op cache does not store the thread, and write, via the micro-op queue, the micro-op from the thread to the micro-op queue responsive to the determination of whether the micro-op cache or the legacy fetch and decode pipeline stores the thread.

What is claimed is: 
     
         1 . A processor comprising:
 a micro-op cache communicatively coupled, via a first write port, to a micro-op queue; and   a legacy fetch and decode pipeline communicatively coupled, via a second write port, to the micro-op queue, the processor to:
 determine, via a first thread select algorithm, whether the micro-op cache stores a thread, the thread comprising a micro-op to be written to the micro-op queue; 
 determine, via a second thread select algorithm, whether the legacy fetch and decode pipeline stores the thread if the micro-op cache does not store the thread; and 
 write, via the micro-op queue communicatively coupled to the first write port corresponding to the micro-op cache or the second write port corresponding to the legacy fetch and decode pipeline, the micro-op from the thread to the micro-op queue in response to the determination of whether the micro-op cache or the legacy fetch and decode pipeline stores the thread. 
   
     
     
         2 . The processor of  claim 1 , further comprising a fetch address generator to:
 select the thread to write the micro-op to the micro-op queue; and   generate an address corresponding to the thread.   
     
     
         3 . The processor of  claim 2 , wherein the fetch address generator determines that the legacy fetch and decode pipeline does not comprise the selected thread, and the fetch address generator selects a second thread, the second thread comprising the micro-op to be written to the micro-op queue. 
     
     
         4 . The processor of  claim 1 , wherein the micro-op cache stores the selected thread, and wherein the micro-op is written, via the first write port, from the selected thread to the micro-op queue. 
     
     
         5 . The processor of  claim 1 , wherein the legacy fetch and decode pipeline is to decode an instruction, and wherein the decoded instruction comprises the micro-op. 
     
     
         6 . The processor of  claim 1 , wherein the micro-op cache is to determine the number of micro-ops to send to the micro-op queue. 
     
     
         7 . The processor of  claim 1 , wherein the processor is operable in single thread mode or multi-thread mode. 
     
     
         8 . The processor of  claim 7 , wherein a single micro-op from the micro-op cache is written to the micro-op queue per cycle in the single thread mode, and wherein micro-ops from the legacy fetch and decode pipeline and the micro-op cache are written in parallel to the micro-op queue per cycle in multi-thread mode. 
     
     
         9 . A method comprising:
 selecting, via a fetch address generator, a first thread from a micro-op cache associated with a first write port;   selecting, via the fetch address generator, a second thread from a legacy fetch and decode pipeline associated with a second write port; and   writing, to a micro-op queue, micro-ops from the first thread and the second thread in parallel.   
     
     
         10 . The method of  claim 9 , wherein a first thread select algorithm corresponding to the fetch address generator is to select, from the micro-op cache, the first thread to write a first micro-op to the micro-op queue. 
     
     
         11 . The method of  claim 9 , wherein a second thread select algorithm corresponding to the fetch address generator is to select the second thread to write, from the legacy fetch and decode pipeline, a second micro-op to the micro-op queue. 
     
     
         12 . The method of  claim 9 , further comprising generating an address corresponding to the first thread and generating an address corresponding to the second thread. 
     
     
         13 . The method of  claim 9 , wherein the micro-ops are written, via the first port and the second port, from the first thread and the second thread to the micro-op queue in parallel. 
     
     
         14 . The method of  claim 9 , wherein the micro-op cache is to store one or more micro-ops, and wherein the one or more micro-ops comprise one or more decoded instructions. 
     
     
         15 . The method of  claim 14 , wherein the micro-op cache is to record the one or more micro-ops from the legacy fetch and decode pipeline. 
     
     
         16 . A system comprising:
 a memory; and   a processor comprising:
 a micro-op cache communicatively coupled, via a first write port, to a micro-op queue; and 
 a legacy fetch and decode pipeline communicatively coupled, via a second write port, to the micro-op queue, the processor to: 
 select, via a first thread select algorithm, a first thread from a micro-op cache associated with a first write port; 
 select, via second thread select algorithm, a second thread from a legacy fetch and decode pipeline associated with a second write port; and 
 write, to a micro-op queue, micro-ops from the first thread and the second thread in parallel. 
   
     
     
         17 . The system of  claim 16 , wherein the micro-ops are written, via the first port and the second port, from the first thread and the second thread to the micro-op queue in parallel. 
     
     
         18 . The system of  claim 16 , wherein the micro-op cache is to store one or more micro-ops, and wherein the one or more micro-ops comprise one or more decoded instructions. 
     
     
         19 . The system of  claim 16 , wherein the micro-op cache is to record one or more micro-ops from the legacy fetch and decode pipeline. 
     
     
         20 . The system of  claim 16 , wherein the processor is operable in single thread mode or multi-thread mode.