Seal ring structure for radio frequency integrated circuits

Abstract

Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.

1. A seal ring for an integrated circuit wherein said seal ring surrounds an active region of the integrated circuit and comprises alternate first and second sections, the first sections are discontinuous and spaced from the active region to form an inner perimeter for surrounding said active region, and the second sections are discontinuous and spaced from the active region to form an outer perimeter for surrounding said active region, said outer perimeter surrounding said inner perimeter. 
     
     
       2. The seal ring according to  claim 1  wherein said integrated circuit further comprises signal pads, ground pads and radio frequency circuits. 
     
     
       3. The seal ring according to  claim 2  wherein a spacing between said seal ring and said signal pads or said radio frequency circuits is greater than a spacing between said seal ring and ground pads. 
     
     
       4. The seal ring according to  claim 3  wherein the spacing between said seal ring and said signal pads or said radio frequency circuits is between about 20 and 50 microns. 
     
     
       5. The seal ring according to  claim 3  wherein the spacing between said seal ring and said ground pads is between about 10 and 30 microns. 
     
     
       6. The seal ring according to  claim 1  wherein a spacing between said first and second sections is between about 10 and 30 microns. 
     
     
       7. The seal ring according to  claim 1  wherein a width of said seal ring is between about 5 and 15 microns. 
     
     
       8. The seal ring according to  claim 1  wherein said active area is a semiconductor device comprising at least one N-well. 
     
     
       9. The seal ring according to  claim 8  wherein said seal ring is electrically connected to said N-well via a contact, a silicide and a source/drain region of said integrated circuit. 
     
     
       10. The seal ring according to  claim 8  wherein said N-well is electrically connected to a positive supply voltage (Vdd). 
     
     
       11. The seal ring according to  claim 1  wherein the first sections do not overlap the second sections. 
     
     
       12. A semiconductor device with a seal ring for an integrated circuit, comprising:
   alternate first and second sections of the seal ring, discontinuous and spaced apart from an active region of the integrated circuit; wherein the first and second sections forms a separate inner perimeter and an outer perimeter for surrounding the active region.      
     
     
       13. The semiconductor device according to  claim 12  wherein said integrated circuit further comprises first pads, second pads and circuits.  
     
     
       14. The semiconductor device according to  claim 13  wherein a spacing between said seal ring and said first pads or said circuits is greater than a spacing between said seal ring and said second pads.  
     
     
       15. The semiconductor device according to  claim 12  wherein said first pads, second pads and circuits respectively comprises signal pads, ground pads and radio frequency circuits.  
     
     
       16. The semiconductor device according to  claim 15  wherein the spacing between said seal ring and said signal pads or said radio frequency circuits is between about  20  and  50  microns.  
     
     
       17. The semiconductor device according to  claim 16  wherein the spacing between said seal ring and said ground pads is between about  10  and  30  microns.  
     
     
       18. The semiconductor device according to  claim 12  wherein said active area is a semiconductor device comprising at least one N- well, and said seal ring is electrically connected to said N - well via a contact, a silicide and a source/drain region of said integrated circuit.    
     
     
       19. The semiconductor device according to  claim 12  wherein the first sections do not overlap the second sections.