Pattern forming method and semiconductor device manufacturing method using the same

Abstract

A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.

What is claimed is: 
     
       1. A method for forming patterns, comprising:
 forming an etch target layer; 
 etching the etch target layer to form a pre-pattern of a plate shape; 
 forming a plurality of spacers over the pre-pattern; 
 forming a blocking layer having a base portion which covers end portions of the spacers, pad-like portions which protrude from the base portion and an opening which exposes the other portions of the spacers and the pre-pattern; and 
 etching the pre-pattern by using the blocking layer and the spacers as a barrier, to form a plurality of line portions and a plurality of pad portions, 
 wherein the base portion of the blocking layer has a shape surrounding the edges of the pre-pattern. 
 
     
     
       2. The method according to  claim 1 , wherein, in the forming of the blocking layer, the pad-like portions protrude from the base portion in a first direction, and are formed to be arranged in a zigzag style in a second direction crossing with the first direction. 
     
     
       3. The method according to  claim 1 , wherein the pad portions and the line portions are portions of bit lines. 
     
     
       4. The method according to  claim 1 , wherein the spacers have a line width smaller than the pad-like portions. 
     
     
       5. The method according to  claim 1 , wherein the forming of the spacers comprises:
 forming a bottom layer over the pre-pattern; 
 forming a top layer over the bottom layer; 
 etching the top layer to form sacrificial patterns of line shapes over the bottom layer; 
 forming the spacers on both sidewalls of the sacrificial patterns; and 
 removing the sacrificial patterns. 
 
     
     
       6. A method for manufacturing a semiconductor device, comprising:
 forming a bit line stack layer over a substrate; 
 etching the bit line stack layer to form a pre-bit line pattern of a plate shape; 
 forming a hard mask layer including a plurality of spacers, over the pre-bit line pattern; 
 forming a blocking layer having a base portion which covers end portions of the spacers, pad-like portions which protrude from the base portion and an opening which exposes the other portions of the spacers and the pre-bit line pattern; 
 etching the pre-bit line pattern by using the blocking layer and the spacers as a barrier, to form a plurality of bit line portions and a plurality of bit line pad portions; and 
 forming contact plugs which are connected to the bit line pad portions. 
 
     
     
       7. The method according to  claim 6 , wherein, in the forming of the blocking layer, the pad-like portions protrude from the base portion in a first direction, and are formed to be arranged in a zigzag style in a second direction crossing with the first direction. 
     
     
       8. The method according to  claim 6 , wherein the spacers have a line width smaller than the pad-like portions. 
     
     
       9. The method according to  claim 6 , wherein the forming of the spacers comprises:
 forming a bottom layer over the pre-bit line pattern; 
 forming a top layer over the bottom layer; 
 etching the top layer to form sacrificial patterns of line shapes over the bottom layer; 
 forming the spacers on both sidewalls of the sacrificial patterns; and 
 removing the sacrificial patterns. 
 
     
     
       10. A method for manufacturing a semiconductor device, comprising:
 forming a stack layer over a substrate including a cell region and a peripheral circuit region; 
 etching a portion of the stack layer to form a gate structure in the peripheral circuit region; 
 etching a remaining portion of the stack layer to form a pre-bit line pattern of a plate shape in the cell region; 
 forming a hard mask layer including a plurality of spacers, over the pre-bit line pattern; 
 forming a blocking layer having a base portion which covers end portions of the spacers, pad-like portions which protrude from the base portion and an opening which exposes the other portions of the spacers and the pre-bit line pattern; 
 etching the pre-bit line pattern by using the blocking layer and the spacers as a barrier, to form a plurality of bit line portions and a plurality of bit line pad portions; and 
 forming contact plugs which are connected to the bit line pad portions. 
 
     
     
       11. The method according to  claim 10 , wherein, in the forming of the blocking layer, the pad-like portions protrude from the base portion in a first direction, and are formed to be arranged in a zigzag style in a second direction crossing with the first direction. 
     
     
       12. The method according to  claim 10 , wherein the spacers have a line width smaller than the pad-like portions. 
     
     
       13. The method according to  claim 10 , wherein the forming of the spacers comprises:
 forming a bottom layer over the pre-bit line pattern; 
 forming a top layer over the bottom layer; 
 etching the top layer to form sacrificial patterns of line shapes over the bottom layer; 
 forming the spacers on both sidewalls of the sacrificial patterns; and 
 removing the sacrificial patterns.