Cell structure of dual port SRAM

Abstract

An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.

1. A dual port static random access memory (SRAM) cell comprising:
 a first pull-up transistor having a first source and a first drain; 
 a second pull-up transistor having a second source and a second drain; 
 a first pull-down transistor comprising:
 a first drain end connected to the first drain of the first pull-up transistor; and 
 a first gate end connected to a gate of the first pull-up transistor; 
 
 a second pull-down transistor comprising:
 a second drain end connected to the second drain of the second pull-up transistor; and 
 a second gate end connected to a gate of the second pull-up transistor; 
 
 wherein the first pull-down transistor comprises:
 a first sub-transistor; and 
 a second sub-transistor, wherein a drain of the first sub-transistor is connected to a drain of the second sub-transistor to form the first drain end, a source of the first sub-transistor is electrically connected to a source of the second sub-transistor by an additional active region to form a first source end, and a gate of the first sub-transistor is connected to a gate of the second sub-transistor to form the first gate end; and 
 
 wherein the second pull-down transistor comprises:
 a third sub-transistor; and 
 a fourth sub-transistor, wherein a drain of the third sub-transistor is connected to a drain of the fourth sub-transistor to form the second drain end, a source of the third sub-transistor is connected to a source of the fourth sub-transistor to form a second source end, and a gate of the third sub-transistor is connected to a gate of the fourth sub-transistor to form the second gate end. 
 
 
   
   
     2. The dual port SRAM cell of  claim 1 , wherein the drains of the first and the second sub-transistors are physically disconnected by an insulating region, and are electrically connected through a metal line and connecting contacts. 
   
   
     3. The dual port SRAM cell of  claim 2 , wherein the sources of the first and the second sub-transistors are physically disconnected by an insulating region, and are electrically connected through a metal line and connecting contacts. 
   
   
     4. The dual port SRAM cell of  claim 1 , wherein a channel region of the first sub-transistor is separated from a channel region of the second sub-transistor by a first insulating region, and a channel region of the third sub-transistor is separated from a channel region of the fourth sub-transistor by a second insulating region. 
   
   
     5. The dual port SRAM cell of  claim 1  further comprising:
 a first and a second pass-gate transistor each having a source/drain connected to the first drain end of the first pull-down transistor; and 
 a third and a fourth pass-gate transistor each having a source/drain connected to the second drain end of the second pull-down transistor, wherein each of the first, the second, the third and the fourth pass-gate transistors further comprises an additional source/drain region connected to a bit-line. 
 
   
   
     6. The dual port SRAM cell of  claim 5 , wherein the first sub-transistor and the first pass-gate transistor share a first active region, the second sub-transistor comprises a second active region, and wherein the first and the second active regions are physically separated by an insulating region. 
   
   
     7. The dual port SRAM cell of  claim 6 , wherein the second active region extends beyond a gate electrode line of the first pass-gate transistor, and wherein the second active region forms a dummy transistor with the gate electrode line. 
   
   
     8. A semiconductor structure comprising:
 a first static random access memory (SRAM) cell comprising:
 a first active region; 
 a second active region parallel to the first active region, wherein longitudinal directions of the first and the second active regions are in a first direction; 
 a first gate poly extending from over the first active region to over the second active region, wherein the first gate poly has a longitudinal direction in a second direction perpendicular to the first direction; 
 a metal line in a metallization layer and electrically connecting a first portion of the first active region and a first portion of the second active region; and 
 a conductive feature electrically connecting a second portion of the first active region and a second portion of the second active region, wherein the second portions of the first and the second active regions are on opposite sides of the first gate poly than the first portions of the first and the second active regions, respectively, wherein the conductive feature comprises a third active region adjoining the second portions of the first and the second active regions, wherein the third active region is only on one side of the first gate poly. 
 
 
   
   
     9. The semiconductor structure of  claim 8 , wherein the conductive feature comprises:
 an additional metal line in a metallization layer; 
 a first contact connecting the additional metal line and the second portion of the first active region; and 
 a second contact connecting the additional metal line and the second portion of the second active region. 
 
   
   
     10. A semiconductor structure comprising:
 a first static random access memory (SRAM) cell comprising:
 a first active region; 
 a second active region parallel to the first active region; 
 a third active region parallel to the first and the second active regions, wherein longitudinal directions of the first, the second, and the third active regions are in a first direction, and wherein the first, the second, and the third active regions are separated one from another; 
 a first gate poly extending from over the first active region to over the second active region, wherein the first gate poly has a longitudinal direction in a second direction perpendicular to the first direction; 
 a second gate poly over the first and the third active regions, wherein the second gate poly is parallel to the first gate poly; 
 a metal line in a metallization layer and electrically connecting a first portion of the first active region and a first portion of the second active region; and 
 a conductive feature electrically connecting a second portion of the first active region and a second portion of the second active region, wherein the second portions of the first and the second active regions are on opposite sides of the first gate poly than the first portions of the first and the second active regions, respectively; and 
 
 a word-line connected to the second gate poly. 
 
   
   
     11. The semiconductor structure of  claim 10 , wherein the second active region is on one side of the second gate poly only. 
   
   
     12. The semiconductor structure of  claim 10 , wherein the second active region extends on two sides of the second gate poly, and wherein the second active region and the second gate poly form a dummy transistor. 
   
   
     13. The semiconductor structure of  claim 10  further comprising:
 a second SRAM cell comprising:
 the first active region; 
 a fourth active region parallel to the first active region, wherein the fourth active region has a longitudinal direction in the first direction, and wherein the fourth active region is physically separated from the second active region; 
 a third gate poly extending from over the first active region to over the fourth active region, wherein the third gate poly has a longitudinal direction in the second direction; 
 a second metal line electrically connecting a third portion of the first active region and a first portion of the fourth active region; and 
 a second conductive feature electrically connecting a fourth portion of the first active region and a second portion of the fourth active region, wherein the fourth portion of the first active region and the second portion of the fourth active region are on opposite sides of the third gate poly than the third portion of the first active region and the first portion of the third active region. 
 
 
   
   
     14. The semiconductor structure of  claim 13  further comprising:
 a third SRAM cell comprising:
 the first active region; 
 a fourth gate poly extending from over the first active region to over the second active region, wherein the metal line is between the first and the fourth gate polys; and 
 a third conductive feature connecting a third portion of the first active region and a third portion of the second active region, wherein the third portions of the first and the second active regions are on opposite sides of the fourth gate poly than the second portions of the first and the second active regions, respectively.