Two-port SRAM with a high speed sensing scheme

Abstract

A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells; and at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell.

1. A static random access memory (SRAM) macro comprising:
 a cell array having one or more two-port SRAM cells addressed by a plurality of bit lines and word lines including write bit lines, complementary write bit lines, and write word lines for write operation and read bit lines and read word lines for read operation; 
 a plurality of reference cells coupled to a read reference bit line separate from the plurality of the bit lines addressing the SRAM cells and a plurality of read word lines for read operation of the SRAM cells; and 
 at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell. 
 
   
   
     2. The SRAM macro of  claim 1 , wherein the reference bit line is not connected to any SRAM cell in the cell array. 
   
   
     3. The SRAM macro of  claim 1 , wherein the reference current is greater than the sensing current when the selected SRAM cell has a low logic state. 
   
   
     4. The SRAM macro of  claim 1 , wherein the reference current is smaller than the sensing current when the selected SRAM cell has a high logic state. 
   
   
     5. The SRAM macro of  claim 1 , further comprising a column selector coupled among the cell array, the reference cells and the sense amplifier for selectively passing the sensing current and the reference current to the sense amplifier. 
   
   
     6. The SRAM macro of  claim 5 , wherein the sense amplifier further comprises a current mirror load coupled to the column selector for converting the sensing current and the reference current into a sensing voltage and a reference voltage, respectively. 
   
   
     7. The SRAM macro of  claim 6 , wherein the sense amplifier further comprises a comparator for comparing the sensing voltage with the reference voltage to generate a high output signal when the sensing voltage is higher than the reference voltage, and a low output signal when the sensing voltage is lower than the reference voltage. 
   
   
     8. A two-port static random access memory (SRAM) device comprising:
 a cell array having one or more two-port SRAM cells addressed by a plurality of bit lines and word lines including write bit lines, complementary write bit lines, and write word lines for write operation and read bit lines and read word lines for read operation; 
 a plurality of reference cells coupled to a read reference bit line separate from the plurality of the bit lines addressing the SRAM cells and a plurality of read word lines for read operation of the SRAM cells; and 
 at least one sense amplifier having a first terminal receiving a sensing current generated by a two-port SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected two-port SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected two-port SRAM cell. 
 
   
   
     9. The two-port SRAM device of  claim 8 , wherein the reference bit line is not connected to any two-port SRAM cell in the cell array. 
   
   
     10. The two-port SRAM device of  claim 8 , wherein the reference current is greater than the sensing current when the selected two-port SRAM cell has a low logic state. 
   
   
     11. The two-port SRAM device of  claim 8 , wherein the reference current is smaller than the sensing current when the selected two-port SRAM cell has a high logic state. 
   
   
     12. The two-port SRAM device of  claim 8 , further comprising a column selector coupled among the cell array, the reference cells and the sense amplifier for selectively passing the sensing current and the reference current to the sense amplifier. 
   
   
     13. The two-port SRAM device of  claim 12 , wherein the sense amplifier further comprises a current mirror load coupled to the column selector for converting the sensing current and the reference current into a sensing voltage and a reference voltage, respectively. 
   
   
     14. The two-port SRAM device of  claim 13 , wherein the sense amplifier further comprises a comparator for comparing the sensing voltage with the reference voltage to generate a high output signal when the sensing voltage is higher than the reference voltage, and a low output signal when the sensing voltage is lower than the reference voltage.