Dual port cell structure

Abstract

Disclosed are improved layouts for memory cell and memory cell arrays. A memory cell array of multiple memory cells connected by signal lines that twist in connecting the array. Further, an eight transistor memory cell that comprises different resistive paths as seen by the signal lines electrically connected to the cell and asymmetric pass devices associated with those resistive paths. Furthermore, an eight transistor memory cell that includes butt contacts.

1. A memory circuit comprising:
 an array of memory cells arranged in one or more rows and one or more columns, wherein each row and each column comprises a plurality of memory cells; 
 at least two signal lines extending along each column of memory cells, each of the two signal lines being electrically connected to first and second terminals of each memory cell in the column; and 
 a cross-sectional area associated with each row, wherein the two signal lines in a first column twist in a first cross-sectional area, wherein the signal lines are bit lines, the memory cells are dual ported, and each column comprises at least two additional bit lines electrically connected to a third and fourth terminal of each cell in the column. 
 
   
   
     2. The memory circuit of  claim 1  wherein said additional bit lines twist in said first cross-sectional area. 
   
   
     3. A memory circuit comprising:
 an array of dual port memory cells arranged in one or more rows and one or more columns, wherein each row and each column comprises a plurality of memory cells; 
 at least two bit lines extending along each column of memory cells, each of the two bit lines being electrically connected to first and second terminals of each memory cell in the column; 
 at least two additional bit lines electrically connected to a third and fourth terminal of each cell in the column; 
 a cross-sectional area associated with each row, wherein two bit lines in a first column twist in a first cross-sectional area; and 
 at least two word lines per row, the first word line being electrically connected to a fifth terminal of each cell in the row, the second word line being electrically connected to a sixth terminal of each cell in the row. 
 
   
   
     4. The memory circuit of  claim 3  wherein each memory cell comprises four pass devices, each of the four pass devices comprising at least two electrodes, and wherein each of the electrodes is connected to at least one of the six terminals. 
   
   
     5. The memory circuit of  claim 4  wherein the memory cells are dual ported SRAMs and the pass devices are transistors with the gate electrodes of two transistors connected to the first word line and the gate electrodes of the other two transistors connected to the second word line in the row, and wherein each memory cell has an aspect ratio of less than a third. 
   
   
     6. The memory circuit of  claim 4  wherein at least one of said memory cells has different associated resistance paths as seen by two of the bit lines. 
   
   
     7. The memory circuit of  claim 4  wherein at least two electrodes for at least two pass devices are butt contact electrodes and wherein each memory cell comprises at least two additional butt contacts. 
   
   
     8. A dual-ported eight transistor memory cell comprising:
 four pass transistors, two pull-up transistors, and two pull-down transistors wherein the connection path between the source node of a first pass transistor and a first pull-down device is a structure of a first resistance and the connection path between the source node of a second pass transistor and a second pull-down device is a structure of a second resistance, wherein the structure of a first resistance is of greater resistance than the structure of a second resistance, and said first and second pass transistors are asymmetrical; 
 four bit lines each electrically connected to one of the pass transistors; and 
 first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors. 
 
   
   
     9. The memory cell of  claim 8  wherein the connection path between the source node of a third pass transistor and a second pull-down device is a structure of a third resistance and the connection path between the source node of a fourth pass transistor and a second pull-down device is a structure of a fourth resistance wherein the structure of a third resistance is of greater resistance than the structure of a fourth resistance, and said third and fourth pass transistors are asymmetrical. 
   
   
     10. The memory cell of  claim 8  wherein said asymmetry is the first pass transistor having a greater channel width than said second pass transistor. 
   
   
     11. The memory cell of  claim 10  wherein said first pass transistor has at least 5% greater channel width than said second pass transistor. 
   
   
     12. The memory cell of  claim 8  wherein said memory cell is connected to a second memory cell in an adjacent row by at least two shared signal lines wherein said signal lines twist in the cross-sectional area associated with the row. 
   
   
     13. The memory cell of  claim 8  wherein the memory cell has at least four butt contact structures comprising two butt contact from pass transistors to pull-down transistors and two butt contacts between pull-up transistors. 
   
   
     14. A dual-ported eight transistor memory cell comprising:
 four pass transistors, two pull-up transistors, and two pull-down transistors, a first butt contact for connecting a first pass transistor and one of the pull-up or pull-down transistors, and a second butt contact connecting a second pass transistor with a second one of the pull-up or pull-down transistors; 
 first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors; and 
 four bit lines, each connecting to one of the pass transistors. 
 
   
   
     15. The memory cell of  claim 14  further comprising:
 a third and fourth butt contact connecting the pull-up or pull-down transistors. 
 
   
   
     16. A dual-ported eight transistor memory cell comprising:
 four pass transistors, two pull-up transistors, and two pull-down transistors, a first butt contact for connecting a first pass transistor and one of the pull-up or pull-down transistors, and a second butt contact connecting a second pass transistor with a second one of the pull-up or pull-down transistors, a third and fourth butt contact connecting the pull-up or pull-down transistors, and wherein the connection path between a first pass transistor and a first pull-down device is a structure of a first resistance and the connection path between the second pass transistor and a second pull-down device is a structure of a second resistance wherein the structure of a first resistance is of greater resistance than the structure of a second resistance; 
 first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors; and 
 four bit lines, each connecting to one of the pass transistors. 
 
   
   
     17. A dual-ported eight transistor memory cell comprising:
 four pass transistors, two pull-up transistors, and two pull-down transistors, a first butt contact for connecting a first pass transistor and one of the pull-up or pull-down transistors, and a second butt contact connecting a second pass transistor with a second one of the pull-up or pull-down transistors and a third and fourth butt contact connecting the pull-up or pull-down transistors; 
 first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors; and 
 four bit lines, each connecting to one of the pass transistors, 
 wherein the butt contacts are standalone holes connecting an active region to a gate layer with no metal layer directly connected to the butt contacts. 
 
   
   
     18. A memory circuit comprising:
 an array of dual port memory cells arranged in rows and columns, wherein each row and each column comprises a plurality of memory cells, wherein at least one of the dual port memory cells comprises a first connection path between a first pass transistor and a first pull-down transistor having a first resistance and a second connection path between a second pass transistor and a second pull-down transistor having a second resistance, wherein the first resistance is greater than the second resistance; and 
 at least two signal lines extending along each column of dual port memory cells, and electrically connected to a plurality of dual port memory cells, wherein the at least two signal lines in a first column twist in a first cross-sectional area. 
 
   
   
     19. A dual-ported memory cell comprising:
 a first connection path between a first pass transistor and a first pull-down transistor having a first resistance; 
 a second connection path between a second pass transistor and a second pull-down transistor having a second resistance, wherein the first resistance is greater than the second resistance. 
 
   
   
     20. The memory cell of  claim 19 , further comprising:
 at least four butt-contacts. 
 
   
   
     21. The memory cell of  claim 19 , wherein the first pass transistor and the second pass transistor are asymmetrical.