Stacked gate field effect transistor (FET) device

Abstract

Within a stacked gate field effect transistor (FET) device, as well as a method for fabrication thereof and a method for operation thereof, there is provided a stacked gate field effect transistor (FET) device comprising a layered stack of a tunneling dielectric layer, a floating gate electrode, an inter-gate electrode dielectric layer and a control gate electrode formed upon a semiconductor substrate. To enhance performance of the stacked gate field effect transistor (FET) device, at least one of: (1) the floating gate electrode is formed with a pointed edge tip at its outer sidewall; (2) the floating gate electrode in formed with a pointed linear recess centered within its linewidth; and (3) a pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.

What is claimed is:  
     
       1. A stacked gate field effect transistor device comprising: 
       a semiconductor substrate having an active region defined therein;  
       a tunneling dielectric layer formed upon the active region of the semiconductor substrate;  
       a floating gate electrode formed upon the tunneling dielectric layer;  
       an inter-gate electrode dielectric layer formed upon the floating gate electrode;  
       a control gate electrode formed upon the inter-gate electrode dielectric layer; and  
       a pair of source/drain regions formed adjacent a pair of opposite edges of the floating gate electrode, wherein  
       the floating gate electrode is formed with a pointed edge tip at its outer sidewall;  
       the floating gate electrode is formed with a pointed linear recess centered within its linewidth; and  
       the pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.  
     
     
       2. The stacked gate field effect transistor device of  claim 1  wherein the tunneling dielectric layer is formed to a thickness of from about 80 to about 100 angstroms. 
     
     
       3. The stacked gate field effect transistor device of  claim 1  wherein the floating gate electrode is formed to a thickness of from about 500 to about 1000 angstroms. 
     
     
       4. The stacked gate field effect transistor device of  claim 1  wherein the control gate electrode is formed to a thickness of from about 1000 to about 2500 angstroms. 
     
     
       5. The stacked gate field effect transistor device of  claim 1  wherein the stacked gate field effect transistor device is an N channel stacked gate field effect transistor device.