Single Crystal Diamond Dies Packaged with Ultrathin Pocketed Semiconductor Wafer

Abstract

A low thermal resistance device package and heatsink assembly may include a device package containing one or more logic elements with the logic elements thermally connected to one or more diamond dies in a manner that provides a thermally conductive connection between the logic elements through the one or more diamond dies and one or more heatsinks. Each heatsink contains one or more chambers configured for a fluid heat transfer medium. A reconstituted wafer product may include a plurality of diamond dies attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond. The first wafer may be a 300 millimeters sized wafer and the diamond dies may include four sector dies arranged in four sectors of the 300 millimeters sized wafer.

1 . A low thermal resistance device package and heatsink assembly, comprising:
 a device package containing one or more logic elements with the one or more logic elements thermally connected to one or more dies containing diamond in a manner that provides a thermally conductive connection between the one or more logic elements through the one or more dies containing diamond; and   one or more heatsinks wherein each heatsink contains one or more chambers configured for a fluid heat transfer medium.   
     
     
         2 . The assembly of  claim 1 , wherein the dies containing diamond are integrated into a reconstituted wafer product, the reconstituted wafer product comprising the one or more dies containing diamond attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond. 
     
     
         3 . The assembly of  claim 1 , wherein the dies containing diamond are integrated into a temporary carrier populated with the one or more dies containing diamond. 
     
     
         4 . The assembly of  claim 1 , wherein the device package includes interconnects between a first logic element and a second logic element horizontally with one or more of the interconnect technologies selected from a list consisting of: interposer, interconnect bridge, redistribution layers, and substrate. 
     
     
         5 . The assembly of  claim 1 , wherein the one or more heatsinks are configured for jet impingement cooling. 
     
     
         6 . The assembly of  claim 5 , wherein the one or more heatsinks configured for jet impingement cooling include a jet cooling system having a separate cooling compartment for each logic element. 
     
     
         7 . The assembly of  claim 6 , wherein each cooling compartment includes one or more jet openings, one or more coolant outlets and sidewalls that isolate the compartment from neighboring compartments. 
     
     
         8 . The assembly of  claim 5 , wherein the one or more heatsinks configured for jet cooling include one cooling compartment for two or more logic elements with all sprayed surfaces in one plane. 
     
     
         9 . The assembly of  claim 5 , wherein the one or more heatsinks configured for jet cooling include one cooling compartment for two or more logic elements with at least one sprayed surface in a different plane than the other(s). 
     
     
         10 . The assembly of  claim 5 , wherein the one or more heatsinks configured for jet cooling include two or more jet impingement coolers, each configured to cool one or more dies containing diamond. 
     
     
         11 . The assembly of  claim 1 , wherein the one or more heatsinks are configured for microchannel cooling. 
     
     
         12 . The assembly of  claim 1 , wherein the one or more heatsinks are configured for immersion cooling. 
     
     
         13 . The assembly of  claim 12  wherein the one or more dies containing diamond have a surface area enhancing coating or component. 
     
     
         14 . The assembly of  claim 1  wherein the one or more heatsinks are coupled to one or more stiffeners configured to stabilize the one or more heatsinks over the one or more dies containing diamond. 
     
     
         15 . The assembly of  claim 14  wherein the one or more stiffeners are connected to a circuit board underneath the one or more dies containing diamond. 
     
     
         16 . The assembly of  claim 14  wherein the one or more stiffeners are connected to a backing bracket behind a circuit board underneath the one or more dies containing diamond. 
     
     
         17 . The assembly of  claim 1  wherein the one or more heatsinks are integrated into the material of a package lid wherein the lid is optionally connected to one or more stiffeners configured to stabilize the one or more heatsinks over the one or more dies containing diamond. 
     
     
         18 . The assembly of  claim 1  wherein the one or more heatsinks are coupled to the top of a lid and wherein the lid is optionally connected to the one or more stiffeners configured to stabilize the one or more heatsinks over the one or more dies containing diamond. 
     
     
         19 . The assembly of  claim 2  wherein the one or more heatsinks are connected to the one or more dies containing diamond integrated into the reconstituted wafer and the fluid heat transfer medium is in direct contact with the one or more dies containing diamond. 
     
     
         20 . The assembly of  claim 19  wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium, contains at least one of diamond, silicon, copper, zinc, and an anti-fouling coating. 
     
     
         21 . The assembly of  claim 19  wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium is patterned to enhance its surface area and/or direct the fluid flow. 
     
     
         22 . The assembly of  claim 3  wherein the one or more heatsinks are connected to the one or more dies containing diamond originated from the temporary carrier and the fluid heat transfer medium is in direct contact with the one or more dies containing diamond. 
     
     
         23 . The assembly of  claim 22  wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium, contains at least one of diamond, silicon, copper, zinc, and an anti-fouling coating. 
     
     
         24 . The assembly of  claim 22  wherein the surface of the one or more dies containing diamond in contact with the fluid heat transfer medium, is patterned to enhance its surface area and/or direct the fluid flow. 
     
     
         25 . The assembly of  claim 1  wherein an outer perimeter of the one or more heatsinks is aligned with an outer perimeter of the device package. 
     
     
         26 . The assembly of  claim 1  wherein an outer perimeter of the one or more heatsinks is aligned with an outer perimeter of the logic elements located closest to the outer perimeter of the device package. 
     
     
         27 . The assembly of  claim 1  wherein the one or more heatsinks are located over the one or more logic elements and surfaces of the one or more logic elements in contact with the fluid heat transfer medium are in the same plane. 
     
     
         28 . The assembly of  claim 1  wherein the one or more heatsinks are located over the one or more logic elements and at least one surface of the surfaces of the one or more logic elements in contact with the fluid heat transfer medium is in a different plane than the other logic element(s). 
     
     
         29 . The assembly of  claim 1  wherein a surface of the one or more dies containing diamond bonded to the one or more logic elements is below the top surface of one or more memory dies. 
     
     
         30 . The assembly of  claim 5  wherein the one or more heatsinks include one or more manifolds, one or more chambers, one or more inlets, and one or more outlets configured for jet impingement cooling with the fluid heat transfer medium in direct contact with the one or more dies containing diamond. 
     
     
         31 . The assembly of  claim 5  wherein the one or more heatsinks include a portion of the dies containing diamond. 
     
     
         32 . The assembly of  claim 11  wherein the one or more heatsinks include horizontal microchannels and vertical vias configured for use with a fluid heat transfer medium wherein the fluid heat transfer medium is in direct contact with a surface of the one or more dies containing diamond. 
     
     
         33 . The assembly of  claim 11  wherein the one or more heatsinks include a portion of the dies containing diamond. 
     
     
         34 . The assembly of  claim 1  wherein the one or more heatsinks include one or more nozzles configured to spray a jet of fluid heat transfer medium against a thermally conductive surface in thermal contact with one or more logic elements. 
     
     
         35 . The assembly of  claim 34  wherein at least one of the one or more nozzles is aligned with a hot spot on at least one logic element. 
     
     
         36 . The assembly of  claim 34  wherein the thermally conductive surface includes one or more patterned structures configured to improve conduction of heat to the fluid heat transfer medium. 
     
     
         37 . The assembly of  claim 36  wherein the one or more patterned structures include fins or pins coupled to the thermally conductive surface. 
     
     
         38 . The assembly of  claim 4  further comprising one or more logic units, and one or more memory units. 
     
     
         39 . The assembly of  claim 12  further comprising a condenser coupled to an outlet in the one or more heatsinks outer casing and wherein the fluid heat transfer medium is a two phase coolant. 
     
     
         40 . The assembly of  claim 12  wherein the one or more heatsinks further include one or more impellers configured to move the fluid heat transfer medium. 
     
     
         41 . The assembly of  claim 12  wherein one or more heatsinks include a fluid heat transfer medium suitable for immersion cooling, and one or more heatsinks include a fluid heat transfer medium suitable for either immersion cooling or alternative fluid heat transfer medium cooling methods. 
     
     
         42 . The assembly of  claim 41  wherein at least two heatsinks use different fluid heat transfer media from one another. 
     
     
         43 . The assembly of  claim 41  wherein at least one heatsink includes one or more nozzles configured to spray the fluid heat transfer medium against a thermally conductive surface thermally connected to one or more logic elements. 
     
     
         44 . The assembly of  claim 41  wherein at least one heatsink includes one or more microchannels and vias configured for microchannel cooling with a fluid heat transfer medium in thermal contact with a thermally conductive surface thermally connected to one or more logic elements. 
     
     
         45 . The assembly of  claim 41  wherein at least one fluid heat transfer medium is a hydrocarbon or fluorochemical. 
     
     
         46 . The assembly of  claim 1  wherein at least one fluid heat transfer medium contains water. 
     
     
         47 . The assembly of  claim 5  wherein at least one fluid heat transfer medium contains water. 
     
     
         48 . The assembly of  claim 2  wherein at least one of the first wafer and second wafer includes one or more pockets containing one or more dies containing diamond and wherein the plurality of dies containing diamond are sandwiched between the first wafer and the second wafer. 
     
     
         49 . The assembly of  claim 48  where the pockets are created in a top layer of the first wafer, or the second wafer or both the first wafer and the second wafer. 
     
     
         50 . The assembly of  claim 49  wherein the top layer contains at least one of the following materials: silicon, germanium, aluminum, tin, copper, silver, gold, zinc, silicon oxide, a sol-gel, polymer, thermoplastic, curable adhesive, molding compound, epoxies, photoresists, benzocyclobutene (BCB) derivatives, spin-on photo-dielectrics, spin-on glass, polymer-derived ceramics, silicones, and polyimides. 
     
     
         51 . The assembly of  claim 48  where at least one of the first wafer and the second wafer is a silicon wafer and the pockets are created in the silicon wafer. 
     
     
         52 . The assembly of  claim 48  where the pockets are created by additive manufacturing. 
     
     
         53 . The assembly of  claim 48  wherein the pockets each envelope at least 90 percent of each of the plurality of dies containing diamond. 
     
     
         54 . The assembly of  claim 48  wherein each pocket completely envelopes a die containing diamond and wherein the first wafer is bonded to the second wafer. 
     
     
         55 . The assembly of  claim 48  wherein the pockets extend 100 micrometers or deeper into at least one of the first wafer and second wafer. 
     
     
         56 . The assembly of  claim 48  wherein the pockets extend less than 100 micrometers but greater than 10 micrometers into at least one of the first wafer and second wafer. 
     
     
         57 . The assembly of  claim 2 , wherein the thermal resistance of the reconstituted wafer product is less than 2 mm 2 -K/W when integrated into a final device package. 
     
     
         58 . The assembly of  claim 2 , wherein the thermal resistance of the reconstituted wafer product is less than 1 mm 2 -K/W when integrated into a final device package. 
     
     
         59 . The assembly of  claim 2 , wherein the thermal resistance of the reconstituted wafer product is less than 0.5 mm 2 -K/W when integrated into a final device package. 
     
     
         60 . The assembly of  claim 2  wherein the dies containing diamond include one or more single crystal diamond (SCD) dies. 
     
     
         61 . The assembly of  claim 60 , wherein the dies containing diamond are all SCD dies. 
     
     
         62 . The assembly of  claim 60 , wherein the one or more SCD dies are characterized by a lateral dimension of 1 centimeter or greater. 
     
     
         63 . The assembly of  claim 2 , wherein the dies containing diamond include at least one polycrystalline diamond die. 
     
     
         64 . The assembly of  claim 2 , wherein the dies containing diamond include at least one composite diamond die comprised of diamond and a metal, wherein the metal includes one or more of the following: copper, silver, gold, aluminum, and zinc. 
     
     
         65 . The assembly of  claim 2 , wherein at least one of the dies containing diamond has a roughness on at least one side of at least 2 nanometers. 
     
     
         66 . The assembly of  claim 2  wherein the dies containing diamond vary in thickness less than 5 micrometers. 
     
     
         67 . The assembly of  claim 2 , wherein first and second wafers are characterized by lateral dimensions corresponding to those of a standard-sized semiconductor wafer. 
     
     
         68 . The assembly of  claim 2 , wherein the first and second wafers are silicon wafers. 
     
     
         69 . The assembly of  claim 2 , wherein at least one of the first and second wafers is characterized by a thickness of less than 100 micrometers. 
     
     
         70 . The assembly of  claim 2 , wherein at least one of the first and second wafers is characterized by a thickness of less than 10 micrometers. 
     
     
         71 . The assembly of  claim 2 , wherein a layer of copper, aluminum, or silicon carbide is sandwiched between the dies containing diamond and a first wafer, wherein the copper, aluminum, or silicon carbide, is at least 100 micrometers thick. 
     
     
         72 . The assembly of  claim 2  wherein the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers by either: thermocompression bonding (TCB), soldering, eutectic bonding, transient liquid phase bonding (TLPB), sintering, surface activated bonding (SAB), atomic diffusion bonding (ADB), plasma assisted bonding (PAB), ultrasonic bonding (UB), brazing, or adhesive bonding. 
     
     
         73 . The assembly of  claim 2  wherein either the first wafer, the second wafer, or both the first wafer and the second wafer are silicon wafers bonded to the dies containing diamond by surface melting the first wafer, the second wafer or both the first wafer and the second wafer. 
     
     
         74 . The assembly of  claim 2  wherein either the first wafer, the second wafer, or both wafers are bonded to the dies containing diamond with a multi-layer material made out of nickel and aluminum, aluminum and titanium, titanium and silicon, boron and titanium, or aluminum and palladium. 
     
     
         75 . The assembly of  claim 2  further comprising a smoothening material coupled to each of the plurality of dies containing diamond, wherein the smoothening material is a semiconductor smoothening layer and the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers by either: surface activated bonding (SAB), atomic diffusion bonding (ADB), plasma assisted bonding (PAB), laser assisted bonding (LAB), Flash Lamp assisted bonding (FLAB), or adhesive bonding. 
     
     
         76 . The assembly of  claim 2  wherein the smoothening material is a dielectric and the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers by either: surface activated bonding (SAB), atomic diffusion bonding (ADB), plasma assisted bonding (PAB), or adhesive bonding. 
     
     
         77 . The assembly of  claim 2 , wherein the dies containing diamond are attached to either: the first wafer, the second wafer, or both wafers using a bond material. 
     
     
         78 . The assembly of  claim 77 , wherein the bond material includes copper, silicon, germanium, silver, zinc, or a dielectric. 
     
     
         79 . The assembly of  claim 2  wherein at least one of the plurality of dies containing diamond are located in an area of the reconstituted wafer product corresponding to a hot spot in one or more logic elements when the reconstituted wafer product is bonded with the one or more logic elements. 
     
     
         80 . The assembly of  claim 2 , wherein at least one of the plurality of dies containing diamond is located in an area of the reconstituted wafer product corresponding to the location of one or more logic elements that are known good dies when the reconstituted wafer product is bonded with the one or more logic elements. 
     
     
         81 . The assembly of  claim 2  further comprising one or more dummy dies sandwiched between the first and second wafer wherein the dummy dies are placed on locations corresponding to one or more logic elements that are not known good dies when the reconstituted wafer product is bonded with the one or more logic elements. 
     
     
         82 . The assembly of  claim 2  further comprising one or more dummy dies sandwiched between the first wafer and the second wafer wherein the dummy dies are placed near an edge of the first wafer and the second wafer. 
     
     
         83 . The assembly of  claim 2  wherein either the first wafer, the second wafer, or both the first wafer and the second wafer are silicon wafers bonded to the dies containing diamond by either laser assisted heating, flash lamp heating, or both. 
     
     
         84 . The assembly of  claim 83  wherein the reconstituted wafer further comprises a heat source absorption layer located at the bond interface wherein the heat source absorption layer contains at least one of the following elements: silicon, germanium, aluminum, tin, copper, silver, or gold. 
     
     
         85 . The assembly of  claim 2  wherein either the first wafer, the second wafer, or both the first wafer and the second wafer are silicon wafers bonded to the dies containing diamond by QCW or CW laser heating. 
     
     
         86 . The assembly of  claim 2 , wherein one or both wafers are silicon wafers, and where the crystal orientation of one or both silicon wafers is either ( 100 ), ( 111 ), or ( 110 ), and the silicon originates from either the Czochralski (CZ) method or the Float Zone (FZ) method. 
     
     
         87 . The assembly of  claim 2 , wherein the gaps are filled partially or completely by one or more of the following methods: plating, plasma spraying, through-hole wafer, pocketed wafer, curable adhesive or polymer, thermoplastic polymer, underfill materials, sealants, spin-on dielectrics. 
     
     
         88 . The assembly of  claim 2 , wherein the two or more dies containing diamond are placed on the first wafer near each other based on matching die thickness resulting in a gradual change in die thickness from wafer side to side, or wafer center to edge. 
     
     
         89 . The assembly of  claim 2 , wherein the one or more dies containing diamond are placed on a first wafer, and the surfaces of the dies containing diamond facing away from the first wafer are deposited with a precursor for bonding to a logic wafer with the precursor containing one of the following: titanium, chromium, nickel, tantalum, or silicon. 
     
     
         90 . A reconstituted wafer product, comprising: a plurality of dies containing diamond attached to at least a first wafer in a manner that provides a thermally conductive connection between the first wafer and the dies containing diamond, wherein the first wafer is a 300 millimeters sized wafer and the plurality of dies containing diamond include four sector dies arranged in four sectors of the 300 millimeters sized wafer. 
     
     
         91 . The product of  claim 90  wherein each of the four sector dies comprises less than an entire quadrant. 
     
     
         92 . The product of  claim 90  wherein each of the four sectors includes a cut corner. 
     
     
         93 . The product of  claim 90  further comprising one or more logic elements formed in the first wafer or the second wafer. 
     
     
         94 . The product of  claim 90 , further comprising one or more vias through the wafer. 
     
     
         95 . The product of  claim 90  compatible with silicon transistor fabrication process conditions. 
     
     
         96 . The assembly of  claim 1  wherein the dies containing diamond each have a thickness of between 100 micrometers and 800 micrometers. 
     
     
         97 . The assembly of  claim 1  wherein at least one of the dies containing diamond has a thermal conductivity higher than 2000 W/m-K. 
     
     
         98 . The assembly of  claim 1  wherein a main surface of at least one of the one or more dies containing diamond includes a crystal orientation of ( 100 ), ( 110 ), ( 111 ), or ( 113 ).