Semiconductor structure and method for forming same, and memory

Abstract

A semiconductor structure includes a substrate, a chip set, a conductive structure and a wire. The substrate includes an external circuit. The chip set is disposed at one side of the substrate and includes a plurality of chip units that are spaced in a direction perpendicular to the substrate, and the chip units are electrically connected to each other. The conductive structure is disposed on at least a surface of at least one of the chip units. One end of the wire is connected to the conductive structure, and the other end extends outside of the chip units and is connected to the external circuit.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate, comprising an external circuit;   a chip set, disposed at one side of the substrate and comprising a plurality of chip units that are spaced in a direction perpendicular to the substrate, wherein the chip units are electrically connected to each other;   a conductive structure, disposed on a surface of at least one of the chip units; and   a wire, wherein one end of the wire is connected to the conductive structure, and another end extends outside of the chip units and is connected to the external circuit.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the conductive structure comprises:
 a redistribution layer, disposed on the surface of the at least one of the chip units;   a connection pad, disposed on a surface of a chip unit on which the redistribution layer is formed and connected to a side of the redistribution layer close to an edge of the chip unit, wherein the wire is connected to the connection pad in a contact manner; and   a first conductive bump, disposed on the surface of the chip unit and connected to the redistribution layer in a contact manner, wherein an orthographic projection of the first conductive bump on the substrate does not overlap with an orthographic projection of the connection pad on the substrate.   
     
     
         3 . The semiconductor structure of  claim 2 , wherein the conductive structure is located on a surface of a chip unit closest to the substrate in the chip set. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein the chip set comprises a first chip unit and a second chip unit that are in mirror arrangement; the second chip unit is located at a side of the first chip unit away from the substrate; and the conductive structure is disposed on a surface of the first chip unit close to the second chip unit. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein a surface of the second chip unit close to the first chip unit is provided with a second conductive bump; the second conductive bump is disposed oppositely to the first conductive bump; and the chip set further comprises:
 a connection portion, located between the first conductive bump and the second conductive bump, wherein the first conductive bump, the connection portion and the second conductive bump separate the first chip unit and the second chip unit by a preset distance.   
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 an insulation filling layer, filling a gap between two adjacent ones of the chip units.   
     
     
         7 . The semiconductor structure of  claim 1 , wherein there are a plurality of chip sets; the plurality of chip sets are distributed in a laminated manner in the direction perpendicular to the substrate; the chip sets are insulated from each other; and each of the chip sets has a corresponding conductive structure and a corresponding wire. 
     
     
         8 . The semiconductor structure of  claim 7 , further comprising:
 an adhesive layer, disposed between the substrate and a chip set closest to the substrate.   
     
     
         9 . The semiconductor structure of  claim 7 , further comprising:
 a plurality of packaging layers, disposed at gaps between the chip sets in a one-to-one correspondence and filling the gaps between the chip sets.   
     
     
         10 . A method for forming a semiconductor structure, comprising:
 providing a substrate, wherein the substrate comprises an external circuit;   forming a chip set on one side of the substrate, wherein the chip set comprises a plurality of chip units that are spaced in a direction perpendicular to the substrate, and the chip units are electrically connected to each other;   forming a conductive structure on a surface of at least one of the chip units; and   forming a wire, wherein one end of the wire is connected to the conductive structure, and another end extends outside of the chip units and is connected to the external circuit.   
     
     
         11 . The method of  claim 10 , wherein the forming a conductive structure on a surface of at least one of the chip units comprises:
 forming a redistribution layer on the surface of the at least one of the chip units;   forming a connection pad on a surface of a chip unit on which the redistribution layer is formed, wherein the connection pad is connected to a side of the redistribution layer close to an edge of the chip unit, and the wire is connected to the connection pad in a contact manner; and   forming a first conductive bump on the surface of the chip unit on which the redistribution layer is formed, wherein the first conductive bump is connected to the redistribution layer in a contact manner, and an orthographic projection of the first conductive bump on the substrate does not overlap with an orthographic projection of the connection pad on the substrate.   
     
     
         12 . The method of  claim 11 , wherein the conductive structure is formed on a surface of a chip unit that is closest to the substrate in the chip set. 
     
     
         13 . The method of  claim 11 , wherein the chip set comprises a first chip unit and a second chip unit that are in mirror arrangement; the second chip unit is formed on a side of the first chip unit away from the substrate; and the conductive structure is formed on a surface of the first chip unit close to the second chip unit. 
     
     
         14 . The method of  claim 13 , further comprising:
 forming a second conductive bump on a surface of the second chip unit close to the first chip unit, wherein the second conductive bump is disposed oppositely to the first conductive bump;   wherein the forming a chip set on one side of the substrate further comprises:   forming a connection portion on a surface of the first conductive bump, wherein the connection portion is located between the first conductive bump and the second conductive bump, and the first conductive bump, the connection portion and the second conductive bump separate the first chip unit and the second chip unit by a preset distance.   
     
     
         15 . The method of  claim 10 , further comprising:
 forming an insulation filling layer, wherein the insulation filling layer fills a gap between two adjacent ones of the chip units.   
     
     
         16 . The method of  claim 10 , wherein there are a plurality of chip sets; the plurality of chip sets are distributed in a laminated manner in the direction perpendicular to the substrate; the chip sets are insulated from each other; and each of the chip sets has a corresponding conductive structure and a corresponding wire. 
     
     
         17 . The method of  claim 16 , further comprising:
 forming an adhesive layer between the substrate and a chip set closest to the substrate.   
     
     
         18 . The method of  claim 16 , further comprising:
 forming a plurality of packaging layers, wherein the packaging layers are disposed at gaps between the chip sets in a one-to-one correspondence and fill the gaps between the chip sets.   
     
     
         19 . A memory, comprising the semiconductor structure of  claim 1 .