US2023144584A1PendingUtilityA1

Method for determining an etch profile of a layer of a wafer for a simulation system

Assignee: ASML NETHERLANDS BVPriority: Jul 26, 2018Filed: Dec 30, 2022Published: May 11, 2023
Est. expiryJul 26, 2038(~12 yrs left)· nominal 20-yr term from priority
G03F 7/705G03F 1/36G06F 30/398G03F 7/70633
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Claims

Abstract

A method for determining an etch profile is described. The method includes determining a masking layer profile. Loading information can be determined. The loading information indicates dependence of an etch rate for the masking layer profile on a quantity and pattern of material being etched. Flux information can be determined. The flux information indicates dependence of the etch rate on an intensity and a spread angle of radiation incident on the masking layer profile. Re-deposition information can be determined. The re-deposition information indicates dependence of the etch rate on an amount of material removed from the masking layer profile that is re-deposited back on the masking layer profile. An output etch profile for the layer of the wafer is determined based on the loading information, the flux information, and/or the re-deposition information.

Claims

exact text as granted — not AI-modified
1 .- 15 . (canceled) 
     
     
         16 . A method comprising:
 calibrating an etch model using experimental cross-section profile information from a layer of a physical wafer generated based on a corresponding etch process;   predicting an etch depth profile of a layer of a modeled wafer based on the calibrated etch model; and   using the predicted etch depth profile to generate or enhance a metrology target design.   
     
     
         17 . The method of  claim 16 , wherein predicting the etch depth profile of the layer of the modeled wafer based on the calibrated etch model comprises:
 determining (i) a starting resist profile for the layer of the wafer and (ii) a resist trim etching recipe;   determining a trimmed resist profile by simulating a trim operation on the starting resist profile according to the resist trim etching recipe; and   determining an output etch depth profile for the layer of the wafer based on the trimmed resist profile.   
     
     
         18 . The method of  claim 17 , further comprising, based at least in part on the trimmed resist profile:
 determining loading information for the trimmed resist profile, the loading information indicating dependence of an etch rate for the trimmed resist profile on a quantity and pattern of material being etched; and/or   determining flux information for the trimmed resist profile, the flux information indicating dependence of the etch rate for the trimmed resist profile on an intensity and a spread angle of radiation incident on the trimmed resist profile; and/or   determining re-deposition information for the trimmed resist profile, the re-deposition information indicating dependence of the etch rate for the trimmed resist profile on an amount of material removed from the trimmed resist profile that is re-deposited back on the trimmed resist profile; and   wherein the determining an output etch depth profile for the layer of the wafer based on the trimmed resist profile comprises determining an output etch depth profile for the layer of the wafer based on the loading information, flux information and/or re-deposition information for the trimmed resist profile.   
     
     
         19 . The method of  claim 16 , wherein enhancing the metrology target design comprises adjusting one or more dimensions and/or a pattern of the metrology target design. 
     
     
         20 . The method of  claim 16 , wherein the experimental cross-section profile information comprises visual or dimensional comparisons between an electronic image of the layer of the physical wafer and a corresponding electronic depiction of the layer generated using the model. 
     
     
         21 . The method of  claim 16 , wherein the using the predicted etch depth profile further comprises using the predicted etch depth profile in rigorous coupled-wave analysis (RCWA) to generate or enhance a metrology target design. 
     
     
         22 . A computer program product comprising a non-transitory computer readable medium having instructions therein, the instructions, when executed by a computer system, configured to cause the computer system to implement the method of  claim 16 . 
     
     
         23 . A method comprising:
 calibrating an etch model for optical proximity correction applications using any combination selected from: cross-section profile, scanning electron microscope, and scatterometry measurements from a layer of a wafer generated based on a corresponding etch process;   predicting an etch parameter of a layer of a modeled wafer based on the calibrated etch model; and   using the predicted etch parameter to correct a photomask, verify a post-etch process window, or co-optimize a lithography illumination and photomask.   
     
     
         24 . The method of  claim 23 , wherein the combination of cross-section profile, scanning electron microscope, and scatterometry measurements include overlay data and alignment data. 
     
     
         25 . The method of  claim 23 , wherein the etch parameter comprises an etch bias of a plurality of patterns of the layer. 
     
     
         26 . The method of  claim 23 , wherein the etch parameter comprises an etch depth profile of the layer. 
     
     
         27 . The method of  claim 26 , wherein predicting the etch depth profile of the layer of the modeled wafer based on the calibrated etch model comprises:
 determining (i) a starting resist profile for the layer of the wafer and (ii) a resist trim etching recipe;   determining a trimmed resist profile by simulating a trim operation on the starting resist profile according to the resist trim etching recipe; and   determining an output etch depth profile for the layer of the wafer based on the trimmed resist profile.   
     
     
         28 . The method of  claim 27 , further comprising, based at least in part on the trimmed resist profile:
 determining loading information for the trimmed resist profile, the loading information indicating dependence of an etch rate for the trimmed resist profile on a quantity and pattern of material being etched; and/or   determining flux information for the trimmed resist profile, the flux information indicating dependence of the etch rate for the trimmed resist profile on an intensity and a spread angle of radiation incident on the trimmed resist profile; and/or   determining re-deposition information for the trimmed resist profile, the re-deposition information indicating dependence of the etch rate for the trimmed resist profile on an amount of material removed from the trimmed resist profile that is re-deposited back on the trimmed resist profile; and   wherein the determining an output etch depth profile for the layer of the wafer based on the trimmed resist profile comprises determining an output etch depth profile for the layer of the wafer based on the loading information, flux information and/or re-deposition information for the trimmed resist profile.   
     
     
         29 . A computer program product comprising a non-transitory computer readable medium having instructions therein, the instructions, when executed by a computer system, configured to cause the computer system to implement the method of  claim 23 . 
     
     
         30 . A method comprising:
 calibrating an etch model for predicting a cross-wafer etch fingerprint as input for wafer inspection or patterning control operations and having parameters that describe cross wafer variations of a corresponding etch process, using any combination selected from: a cross-wafer cross-section profile, scanning electron microscope, and scatterometry measurements from a layer of a wafer generated based on the etch process;   predicting an etch parameter of a layer of a modeled wafer based on the calibrated etch model; and   using the predicted etch parameter as input for defect prediction of an inspection system, or to a pattern fidelity control system to improve across wafer patterning performance.   
     
     
         31 . The method of  claim 30 , wherein the combination of cross-section profile, scanning electron microscope, and scatterometry measurements include overlay data and alignment data. 
     
     
         32 . The method of  claim 30 , wherein the etch parameter comprises an etch bias of a plurality of patterns of the layer. 
     
     
         33 . The method of  claim 30 , wherein the etch parameter comprises an etch depth profile of the layer. 
     
     
         34 . The method of  claim 33 , wherein predicting the etch depth profile of the layer of the modeled wafer based on the calibrated etch model comprises:
 determining (i) a starting resist profile for the layer of the wafer and (ii) a resist trim etching recipe;   determining a trimmed resist profile by simulating a trim operation on the starting resist profile according to the resist trim etching recipe; and   determining an output etch depth profile for the layer of the wafer based on the trimmed resist profile.   
     
     
         35 . A computer program product comprising a non-transitory computer readable medium having instructions therein, the instructions, when executed by a computer system, configured to cause the computer system to implement the method of  claim 30 .

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