Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate;   a buried gate structure in the substrate, wherein the buried gate structure comprises:
 a gate dielectric layer formed on sidewalls and a bottom surface of a trench in the substrate, wherein the trench extends downward in the substrate; 
 a barrier layer in the trench and on sidewalls and a bottom surface of the gate dielectric layer; 
 a first work function layer in the trench, wherein the first work function layer comprises:
 a main portion in a lower portion of the trench, wherein the barrier layer surrounds sidewalls and a bottom surface of the main portion; and 
 a protruding portion on the main portion and connecting the main portion, wherein an area of a top surface of the protruding portion is less than an area of a bottom surface of the protruding portion; 
 
 a second work function layer at opposite sides of the protruding portion of the first work function layer; and 
   an insulating layer in the trench, wherein the insulating layer is formed on the protruding portion of the first work function layer and on the second work function layer.   
     
     
         2 . The semiconductor structure as claimed in  claim 1 , wherein a width of the protruding portion of the first work function layer gradually increases from the top surface of the protruding portion toward the bottom surface of the protruding portion of the first work function layer. 
     
     
         3 . The semiconductor structure as claimed in  claim 1 , wherein the top surface of the protruding portion of the first work function layer is level with a top surface of the second work function layer. 
     
     
         4 . The semiconductor structure as claimed in  claim 1 , wherein the second work function layer covers a top surface of the barrier layer. 
     
     
         5 . The semiconductor structure as claimed in  claim 1 , wherein an area of a top surface of the second work function layer is greater than an area of a bottom surface of the second work function layer. 
     
     
         6 . The semiconductor structure as claimed in  claim 1 , wherein two opposite side surfaces of the second work function layer are slanted to a top surface of the second work function layer. 
     
     
         7 . A method of manufacturing a semiconductor structure, comprising:
 providing a substrate, and forming a trench extending downward in the substrate;   forming a gate dielectric layer on sidewalls and a bottom surface of the trench;   forming a barrier layer on a lower portion of sidewalls and a bottom surface of the gate dielectric layer;   forming a first work function layer on a lower portion of the trench, wherein the first work function layer comprises:
 a main portion in the lower portion of the trench, wherein the barrier layer surrounds sidewalls and a bottom surface of the main portion; and 
 a protruding portion on the main portion and connecting the main portion, wherein an area of a top surface of the protruding portion is less than an area of a bottom surface of the protruding portion; 
   forming a second work function layer at opposite sides of the protruding portion of the first work function layer; and   forming an insulating layer on the protruding portion of the first work function layer and on the second work function layer.   
     
     
         8 . The method of manufacturing the semiconductor structure as claimed in  claim 7 , wherein forming the barrier layer and forming the first work function layer comprise:
 forming a barrier material layer on the gate dielectric layer;   forming a first work function material layer on the barrier material layer;   recessing the first work function material layer to form a recessed first work function material layer;   forming a mask on the recessed first work function material layer, wherein the mask exposes a portion of a top surface of the recessed first work function material layer;   performing an etching step by using the mask to remove the portion of the recessed first work function material layer that is not covered by the mask, thereby forming the first work function layer; and   removing the mask.   
     
     
         9 . The method of manufacturing the semiconductor structure as claimed in  claim 8 , wherein an upper portion of sidewalls of the barrier material layer is exposed in the trench after the first work function material layer is recessed, and wherein forming the mask comprises:
 conformably depositing a first dielectric material layer on a top surface and the upper portion of sidewalls of the barrier material layer, wherein the first dielectric material layer forms an opening in the trench;   filling the opening with a second dielectric material layer; and   removing a portion of the first dielectric material layer that is not covered by the second dielectric layer to form the mask,   wherein the mask comprises a portion of the second dielectric material layer that fills the opening and a remaining portion of the first dielectric material layer.   
     
     
         10 . The method of manufacturing the semiconductor structure as claimed in  claim 9 , wherein the mask comprises:
 a first dielectric layer on the recessed first work function material layer; and   a second dielectric layer on the first dielectric layer,   wherein sidewalls of the first dielectric layer are level with sidewalls of the second dielectric layer.   
     
     
         11 . The method of manufacturing the semiconductor structure as claimed in  claim 9 , wherein one of the first dielectric material layer or the second dielectric material layer is an oxide material layer, and the other of the first dielectric material layer or the second dielectric material layer is a nitride material layer. 
     
     
         12 . The method of manufacturing the semiconductor structure as claimed in  claim 8 , wherein after the first work function layer is formed, a portion of the barrier material layer is removed, and the remaining portion of the barrier material layer forms a barrier layer, and
 wherein a top surface of the barrier layer is level with the bottom surface of the protruding portion of the first work function layer.   
     
     
         13 . The method of manufacturing the semiconductor structure as claimed in  claim 7 , wherein a width of the protruding portion of the first work function layer gradually increases from the top surface of the protruding portion toward the bottom surface of the protruding portion of the first work function layer. 
     
     
         14 . The method of manufacturing the semiconductor structure as claimed in  claim 7 , wherein the top surface of the protruding portion of the first work function layer is level with a top surface of the second work function layer. 
     
     
         15 . The method of manufacturing the semiconductor structure as claimed in  claim 7 , wherein the second work function layer covers the top surface of the barrier layer. 
     
     
         16 . The method of manufacturing the semiconductor structure as claimed in  claim 7 , wherein two opposite side surfaces of the second work function layer are slanted to a top surface of the second work function layer.