Memory device with predetermined start-up value

Abstract

A method for making a semiconductor memory device comprising a plurality of memory cells for storing one or more data values, the method comprising; exposing a pattern on a wafer for creating structures for a plurality of memory cells for the semiconductor memory device, wherein the pattern is exposed by means of one or more charged particle beams; and varying an exposure dose of the one or more charged particle beams during exposure of the pattern to generate a set of one or more non-common features in one or more structures of at least one of the memory cells, so that the structures of the at least one memory cell differ from the corresponding structures of other memory cells of the semiconductor memory device.

1 - 15 . (canceled) 
     
     
         16 . A semiconductor memory device comprising a plurality of memory cells for storing one or more data values,
 wherein the semiconductor memory device is a member of a set of semiconductor memory devices,   wherein each semiconductor memory device of the set has a same number of memory cells as all of the other semiconductor memory devices of the set, and the memory cells of each semiconductor memory device of the set has a same structure as the memory cells of all of the other semiconductor memory devices of the set except for a set of one or more non-common features,   wherein the set of semiconductor memory devices comprises a plurality of subsets of semiconductor memory devices, each semiconductor memory device of the set being a member of only one of the subsets,   wherein the semiconductor memory device stores an initial data value upon power-up of the semiconductor memory device,   wherein the initial data value is determined at least in part by the set of non-common features of the semiconductor memory device, and   wherein the initial data value of the semiconductor memory device is the same as the initial data value of the semiconductor memory devices in each subset and is different from the initial data value of the semiconductor memory devices in every other subset.   
     
     
         17 . The semiconductor memory device according to  claim 16 , wherein the set of non-common features includes a gate of a transistor forming part of one of the memory cells of the semiconductor memory device. 
     
     
         18 . The semiconductor memory device according  claim 16 , wherein the set of non-common features includes an active region of a transistor or diode forming part of one of the memory cells of the semiconductor memory device. 
     
     
         19 . (canceled) 
     
     
         20 . (canceled) 
     
     
         21 . The semiconductor memory device of  claim 17 , wherein a width and/or a length of the gate is the same as a corresponding width and/or length of the gate of a corresponding transistor of the semiconductor memory devices in each subset, and is different from a corresponding width and/or length of the gate of a corresponding transistor of the semiconductor memory devices in every other subset. 
     
     
         22 . The semiconductor memory device of  claim 18 , wherein an N+ or P+ doping of the active region is the same as a corresponding active region of a corresponding transistor of the semiconductor memory devices in each subset, and is different from a corresponding active region of a corresponding transistor of the semiconductor memory devices in every other subset. 
     
     
         23 . The semiconductor memory device according to  claim 22 , wherein the transistor or diode of the semiconductor memory device is non-functional as a result of the N+ or P+ doping of the active region of the circuit element. 
     
     
         24 . The semiconductor memory device according to  claim 16 , wherein the set of non-common features includes one of a plurality of non-functional transistors and a plurality of non-functional diodes. 
     
     
         25 . The semiconductor memory device according to  claim 16 , wherein the semiconductor memory device comprises a ROM device, and a data content of the ROM device is determined in part by the set of non-common features. 
     
     
         26 . The semiconductor memory device according to  claim 16 , wherein the semiconductor memory device comprises an SRAM device, and the set of non-common features includes a plurality of non-functional inverter transistors of the SRAM device. 
     
     
         27 . The semiconductor memory device according to  claim 16 , wherein the set of non-common features is created in part by an exposure dose variation of a charged-particle beam during manufacture of the semiconductor memory device. 
     
     
         28 . The semiconductor memory device according to  claim 27 , wherein the dose variation is derived from application of a dose modulation map to design layout related data used to prepare pattern data for controlling the charged particle beams. 
     
     
         29 . The semiconductor memory device according to  claim 28 , wherein the dose modulation map defines an absolute dose to be applied at a predefined portion of the pattern. 
     
     
         30 . A maskless pattern writer such as a charged particle multi-beamlet lithography machine, configured to expose a pattern on a surface of a target such as a wafer for making the semiconductor memory device of  claim 16 . 
     
     
         31 . A semiconductor memory device comprising a plurality of memory cells for storing one or more data values,
 wherein structures for the plurality of memory cells comprise one or more common features of a plurality of the memory cells and a set of one or more non-common features in one or more of the structures of at least one of the memory cells, so that the structures of the at least one memory cell differ from the corresponding structures of other memory cells of the semiconductor memory device;   wherein the semiconductor memory device stores an initial data value upon power-up of the semiconductor memory device, and   wherein the initial data value is determined at least in part by the set of non-common features of the semiconductor memory device.   
     
     
         32 . The semiconductor memory device according to  claim 31 , wherein the set of non-common features includes a gate of a transistor forming part of one of the memory cells of the semiconductor memory device. 
     
     
         33 . The semiconductor memory device according to  claim 31 , wherein the set of non-common features includes an active region of a transistor or diode forming part of one of the memory cells of the semiconductor memory device. 
     
     
         34 . The semiconductor memory device according to  claim 33 , wherein the transistor or diode is non-functional as a result of N+ or P+ doping of the active region. 
     
     
         35 . The semiconductor memory device according to  claim 31 , wherein the set of non-common features includes one of a plurality of non-functional transistors and a plurality of non-functional diodes. 
     
     
         36 . The semiconductor memory device according to  claim 31 , wherein the semiconductor memory device comprises a ROM device, and a data content of the ROM device is determined in part by the set of non-common features. 
     
     
         37 . The semiconductor memory device according to  claim 31 , wherein the semiconductor memory device comprises an SRAM device, and the set of non-common features includes a plurality of non-functional inverter transistors of the SRAM device.