Iii-v semiconductor devices with selective oxidation

Abstract

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

1 . (canceled) 
     
     
         2 . A method of fabricating a semiconductor device, the method comprising:
 providing a stack of two layers disposed on a base layer, wherein a first layer of the two layers is an oxidized layer;   forming a dummy gate;   forming source and drain regions in contact with sides of the two layers;   removing the dummy gate to provide a gate opening;   etching the first layer through the gate opening to provide a lower gate region; and   forming a replacement gate between a plurality of walls, the replacement gate comprising an upper gate portion having a first width and a lower gate portion having a second width, wherein the lower gate portion is located in the lower gate region below the upper gate portion, and wherein the second width is greater than the first width.   
     
     
         3 . The method of  claim 2 , wherein providing the stack of two layers disposed on the base layer comprises:
 depositing two crystalline semiconductor layers on the base layer; and   selectively oxidizing one of the two crystalline semiconductor layers to provide the first layer.   
     
     
         4 . The method of  claim 3 , wherein selectively oxidizing the one of the two crystalline semiconductor layers comprises:
 exposing the semiconductor substrate in water vapor at a temperature in a range of approximately 350 degrees to approximately 550 degrees Celsius.   
     
     
         5 . The method of  claim 3 , wherein the two crystalline semiconductor layers comprise a semiconducting material selected from a group consisting of indium gallium arsenide (InGaAs) and gallium arsenide (GaAs). 
     
     
         6 . The method of  claim 3 , further comprising:
 performing shallow trench isolation within the base layer to form a plurality of trenches exposing the first layer and a second layer; and   depositing an insulator into the plurality of trenches.   
     
     
         7 . The method of  claim 2 , further comprising:
 depositing a high-K insulator around at least part of the replacement gate.   
     
     
         8 . The method of  claim 2 , wherein the base layer comprises germanium (Ge). 
     
     
         9 . The method of  claim 8 , wherein the Ge has a thickness in a range of approximately 100 nanometers to approximately 1 micrometer. 
     
     
         10 . A method of fabricating a semiconductor device, the method comprising:
 disposing a stack of two crystalline semiconductor layers on a base layer;   selectively oxidizing a first of the two crystalline semiconductor layers to provide a first layer;   removing a dummy gate structure to provide a gate opening;   etching the first layer through the gate opening to provide a lower gate region; and   forming a replacement gate between a plurality of walls, the replacement gate comprising an upper gate portion having a first width and a lower gate portion having a second width, wherein the lower gate portion is located in the lower gate region, and wherein the second width is greater than the first width.   
     
     
         11 . The method of  claim 10 , further comprising:
 forming source and drain regions in contact with the first layer and a second layer of the two crystalline semiconductor layers.   
     
     
         12 . The method of  claim 10 , wherein selectively oxidizing the first of the two crystalline semiconductor layers comprises:
 exposing the semiconductor substrate in water vapor at a temperature in range of approximately 350 degrees to approximately 550 degrees Celsius.   
     
     
         13 . The method of  claim 10 , wherein the stack of two crystalline semiconductor layers comprises a semiconducting material selected from a group consisting of indium gallium arsenide (InGaAs) and gallium arsenide (GaAs). 
     
     
         14 . The method of  claim 10 , further comprising:
 performing shallow trench isolation within the base layer to form a plurality of trenches exposing the first layer and a second layer of the two crystalline semiconductor layers; and   depositing an insulator into the plurality of trenches of the base layer.   
     
     
         15 . The method of  claim 10 , further comprising:
 depositing a high-K insulator around at least part of the replacement gate.   
     
     
         16 . The method of  claim 10 , wherein the base layer comprises germanium (Ge). 
     
     
         17 . The method of  claim 16 , wherein the Ge has a thickness in a range of approximately 100 nanometers to approximately 1 micrometer. 
     
     
         18 . A method of fabricating a semiconductor device, the method comprising:
 providing a stack of two layers disposed on a base layer, wherein a first layer of the two layers is an oxidized layer;   forming source and drain regions in contact with sides of the two layers;   removing a dummy gate to provide a gate opening;   etching the first layer through the gate opening to provide a lower gate region; and   forming a replacement gate between a plurality of walls, the replacement gate comprising an upper gate portion having a first width and a lower gate portion having a second width, wherein the lower gate portion is located in the lower gate region, and wherein the second width is greater than the first width.   
     
     
         19 . The method of  claim 18 , wherein providing the stack of two layers disposed on the base layer comprises:
 depositing two crystalline semiconductor layers on the base layer; and   selectively oxidizing one of the two crystalline semiconductor layers to provide the first layer.   
     
     
         20 . The method of  claim 19 , further comprising:
 performing shallow trench isolation within the base layer to form a plurality of trenches exposing the first layer and a second layer of the two crystalline semiconductor layers; and   depositing an insulator into the plurality of trenches of the base layer.   
     
     
         21 . The method of  claim 20 , further comprising:
 depositing a high-K insulator around at least part of the replacement gate.